STACKED SEMICONDUCTOR PACKAGE AND METHOD PRODUCING SAME

• US 20040021229A1
• Filed: 08/02/2002
• Published: 02/05/2004
• Est. Priority Date: 08/02/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsman, Larry D.
• Granted Patent: US 6,700,206 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is adhered to the underside of the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die may be adhered to the upper side of the die paddle along a surface which is opposite to its active surface and is electrically coupled with one or more of the plurality of lead fingers. The die paddle may be formed to exhibit a smaller peripheral outline than that of the first semiconductor die such that the die paddle does not interfere with any peripherally located bond pads of the first semiconductor die. The die paddle may further serve as a heat spreader, resulting in a more thermally stable package.

Claims

1. A semiconductor device package comprising:

a lead frame including a die paddle and a plurality of lead fingers; and

a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface, wherein the active surface of the first semiconductor die is adhered to an underside of the die paddle, and wherein at least one of the plurality of bond pads is electrically connected to at least one of the plurality of lead fingers.

2. The semiconductor device package of claim 1, further comprising an amount of insulating material encapsulating the first semiconductor die, the die paddle and a portion of each of the plurality of lead fingers.

3. The semiconductor device package of claim 1, wherein the die paddle exhibits a peripheral outline which is smaller than a peripheral outline of the first semiconductor die.

4. The semiconductor device package of claim 1, further comprising a second semiconductor die having an active surface, a surface opposing the active surface and a plurality of bond pads on the active surface, wherein the surface opposing the active surface is adhered to an upper side of the die paddle and wherein at least one of the plurality bond pads of the second semiconductor die is electrically connected to at least one of the lead fingers.

5. The semiconductor device package of claim 4, wherein the second semiconductor die is substantially identical to the first semiconductor die.

6. The semiconductor device package of claim 4, wherein the second semiconductor die is substantially the same size as the first semiconductor die.

7. The semiconductor device package of claim 4, wherein the second semiconductor die exhibits a smaller size than the first semiconductor die.

8. The semiconductor device package of claim 7, wherein the second semiconductor die exhibits substantially identical circuitry to that of the first semiconductor die.

9. The semiconductor device package of claim 4, wherein the at least one bond pad of the first semiconductor die corresponds in location on its respective semiconductor die with the at least one bond pad of the second semiconductor die and wherein the at least one bond pad of the first semiconductor die and the at least one bond pad of the second semiconductor die are electrically connected with a common lead finger of the plurality of lead fingers.

10. The semiconductor device package of claim 4, further comprising a volume of dielectric material encapsulating the first semiconductor die, the second semiconductor die, the die paddle and a portion of each of the plurality of lead fingers.

11. The semiconductor device package of claim 1, wherein the first semiconductor die is adhered to the die paddle with a thermally conductive material.

12. The semiconductor device package of claim 1, wherein the lead frame further comprises at least one tie bar coupled with the die paddle and wherein the at least one tie bar is configured and located so as to pass through a stay out zone, remaining clear of any electrical interconnection between the plurality of bond pads and the plurality of lead fingers.

13. The semiconductor device package of claim 1, further comprising at least one alignment feature formed in the lead frame.

14. The semiconductor device package of claim 13, wherein the at least one alignment feature includes a cutout in a portion of the lead frame.

15. The semiconductor device package of claim 13, wherein the at least one alignment feature includes a protuberance formed in a portion of the lead frame.

16. The semiconductor device package of claim 13, wherein the at least one alignment feature is formed in at least one tie bar of the lead frame.

17. The semiconductor device package of claim 1, wherein the die paddle defines at least one opening therein, the at least one opening being configured and located to provide access to the at least one bond pad of the plurality of bond pads.

18. A semiconductor device package comprising:

a lead frame including a centrally located die paddle and a plurality of lead fingers arranged about a periphery of the die paddle;

a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface, wherein a portion of the active surface of the first semiconductor die is adhered to an underside of the die paddle;

a second semiconductor die having an active surface, a second opposing surface, and a plurality of bond pads disposed on the active surface thereof, wherein the second opposing surface of the second semiconductor die is adhered to an upper side of the die paddle;

a first electrical connection between a first bond pad of the plurality of bond pads of the first semiconductor die and a first lead finger of the plurality of lead fingers;

a second electrical connection between a first bond pad of the plurality of bond pads of the second semiconductor die and a second lead finger of the plurality of lead fingers.

19. The semiconductor device package of claim 18, further comprising a volume of dielectric material encapsulating the first semiconductor die, the second semiconductor die, the die paddle of the lead frame and a portion of each of the plurality of lead fingers.

20. The semiconductor device package of claim 19, wherein the first electrical connection and the second electrical connection each comprise a wire bond.

21. The semiconductor device package of claim 20, wherein the active surface of the first semiconductor die is adhered to the underside of the die paddle with an amount of adhesive comprising a thermally conductive material.

22. The semiconductor device package of claim 21, wherein the second opposing surface of the second semiconductor die is adhered to the upper side of the die paddle with another amount of adhesive comprising a thermally conductive material.

23. The semiconductor device package of claim 20, wherein the first semiconductor die is substantially identical to the second semiconductor die.

24. The semiconductor device package of claim 20, wherein the die paddle exhibits a peripheral outline which is smaller than a peripheral outline of the first semiconductor die.

25. The semiconductor device package of claim 24, further comprising at least one alignment feature formed in a portion of the lead frame.

26. The semiconductor device package of claim 25, further comprising at least one tie bar extending from the die paddle, wherein the at least one alignment feature is formed in the at least one tie bar.

27. The semiconductor device package of claim 18, wherein the die paddle defines at least one opening therein, wherein the first electrical connection passes through the at least one opening.

28. A method of forming a semiconductor device package, the method comprising:

providing a lead frame having a die paddle and a plurality of lead fingers;

adhering an active surface of a first semiconductor die to an underside of the die paddle; and

electrically connecting at least one of a plurality of bond pads formed on the active surface of the first semiconductor die to a first lead finger of the plurality of lead fingers.

29. The method according to claim 28, further comprising:

adhering a surface to which is opposed to an active surface of a second semiconductor die to an upper side of the die paddle; and

electrically connecting at least one of a plurality of bond pads formed on the active surface of the second semiconductor die to a second lead finger of the plurality of lead fingers.

30. The method according to claim 29, further comprising encapsulating the first semiconductor die, the second semiconductor die, the die paddle and a portion of each of the plurality of lead fingers with a dielectric material.

31. The method according to claim 28, further comprising forming the die paddle with a peripheral outline which is smaller than a peripheral outline of the first semiconductor die.

32. The method according to claim 28, further comprising forming at least one alignment mark in a portion of the lead frame.

33. The method according to claim 32, wherein forming at least one alignment mark includes forming the at least one alignment mark in a tie bar which extends from the die paddle.

34. The method according to claim 28, wherein adhering the active surface of the first semiconductor die further includes disposing a thermally conductive material between the active surface of the first semiconductor die and the die paddle.

35. The method according to claim 28, further comprising forming at least one opening in the die paddle and locating the at least one opening so as to provide access to at least one bond pad of the plurality of bond pads.

36. A memory device comprising:

a carrier substrate;

a plurality of electrical contacts coupled with electrical circuitry formed in the carrier substrate; and

at least one semiconductor device package coupled with the electrical circuitry in the carrier substrate, the at least one semiconductor device package comprising;

a lead frame including a die paddle and a plurality of lead fingers; and

a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface, wherein the active surface of the first semiconductor die is adhered to an underside of the die paddle, and wherein at least one of the plurality of bond pads is electrically connected to at least one of the plurality of lead fingers.

37. The memory device of claim 36, wherein the at least one semiconductor device package further comprises a second semiconductor die having an active surface, a surface opposing the active surface and a plurality of bond pads on the active surface, wherein the surface opposing the active surface is adhered to an upper side of the die paddle and wherein at least one of the plurality bond pads of the second semiconductor die is electrically connected to at least one of the lead fingers.

38. The memory device of claim 37, wherein the at least one semiconductor device package further comprises an amount of insulating material encapsulating the first semiconductor die, the second semiconductor die, the die paddle and a portion of each of the plurality of lead fingers.

39. The memory device of claim 38, wherein the second semiconductor die is substantially identical to the first semiconductor die.

40. The memory device of claim 39, wherein the at least one bond pad of the first semiconductor die corresponds in location on its respective semiconductor die with the at least one bond pad of the second semiconductor die and wherein the at least one bond pad of the first semiconductor die and the at least one bond pad of the second semiconductor die are electrically connected with a common lead finger of the plurality of lead fingers.

41. The memory device of claim 38, wherein the first semiconductor die and the second semiconductor die are adhered to the die paddle with a thermally conductive material.

42. The memory device of claim 38, wherein the lead frame further comprises at least one tie bar coupled with the die paddle and wherein the at least one tie bar is configured and located so as to pass through a stay out zone, remaining clear of any electrical interconnection between the plurality of bond pads of the first semiconductor die and the plurality of lead fingers.

43. The memory device of claim 42, further comprising at least one alignment feature formed in the at least one tie bar.

44. The memory device of claim 38, further comprising at least one alignment feature formed in a portion of the lead frame.

45. A computing system comprising:

a carrier substrate;

a processor operably coupled to the carrier substrate;

at least one input device operably coupled with the carrier substrate;

at least one output device operably coupled with the carrier substrate; and

a memory device operably coupled to the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising;

a lead frame including a die paddle and a plurality of lead fingers; and

a first semiconductor die having an active surface and a plurality of bond pads disposed on the active surface, wherein the active surface of the first semiconductor die is adhered to an underside of the die paddle, and wherein at least one of the plurality of bond pads is electrically connected to at least one of the plurality of lead fingers.

46. The computing system of claim 45, wherein the at least one semiconductor device package further comprises a second semiconductor die having an active surface, a surface opposing the active surface and a plurality of bond pads on the active surface, wherein the surface opposing the active surface is adhered to an upper side of the die paddle and wherein at least one of the plurality bond pads of the second semiconductor die is electrically connected to at least one of the lead fingers.

47. The computing system of claim 46, wherein the at least one semiconductor device package further comprises a volume of dielectric material encapsulating the first semiconductor die, the second semiconductor die, the die paddle and a portion of each of the plurality of lead fingers.

48. The computing system of claim 47, wherein the second semiconductor die is substantially identical to the first semiconductor die.

49. The computing system of claim 48, wherein the at least one bond pad of the first semiconductor die corresponds in location on its respective semiconductor die with the at least one bond pad of the second semiconductor die and wherein the at least one bond pad of the first semiconductor die and the at least one bond pad of the second semiconductor die are electrically connected with a common lead finger of the plurality of lead fingers.

50. The computing system of claim 47, wherein the first semiconductor die and the second semiconductor die are adhered to the die paddle with a thermally conductive material.

51. The computing system of claim 47, wherein the lead frame further comprises at least one tie bar coupled with the die paddle and wherein the at least one tie bar is configured and located so as to pass through a stay out zone, remaining clear of any electrical interconnection between the plurality of bond pads of the first semiconductor die and the plurality of lead fingers.

52. The computing system of claim 51, further comprising at least one alignment feature formed in the at least one tie bar.

53. The computing system of claim 47, further comprising at least one alignment feature formed in a portion of the lead frame.