Vertical conduction flip-chip device with bump contacts on single surface

• US 20040021233A1
• Filed: 07/03/2003
• Published: 02/05/2004
• Est. Priority Date: 02/10/2000
• Status: Abandoned Application

• Current Assignee: Multiple Shift Key Incorporated
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Sammon, Tima, Kinzer, Daniel M., Arzumanyan, Aram
• Application Number:
  US10/613,326
• Publication Number:
  US 20040021233A1
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/13034 Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Claims

1. A flip chip semiconductor device comprising a silicon wafer having parallel first and second major surfaces;

at least one P region and at least one N region in said wafer which meet at a PN junction within said silicon wafer;

first and second coplanar, laterally spaced and metallized layers formed on said first major surface and insulated form one another and connected to said P region and said N region respectively; and

a bottom metallized layer extending across said second major surface.

2. The device of claim 1 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers;

said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.

3. The device of claim 1 which further includes at least one contact bump connected to each of said metallized layers.

4. The device of claim 2 which further includes at least one contact bump connected to each of said metallized layers.

5. The device of claim 1 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.

6. The device of claim 2 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.

7. The device of claim 2 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.

8. The device of claim 4 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.

9. The device of claim 2 wherein a plurality of contact bumps are connected to each of said first and second metallized layers;

said plurality of contact bumps connected to said first metallized layer being aligned along a first straight row;

said plurality of contact bumps connected to said second metallized layer being aligned along a second straight row.

10. The device of claim 9 wherein said first and second rows are parallel to one another.

11. The device of claim 9 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers;

said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.

12. A flip chip semiconductor device comprising a silicon wafer having first and second parallel major surfaces;

at least one P region and at least one N region in said wafer which meet at a PN junction within said silicon wafer;

first and second coplanar, laterally spaced metallized layers formed on said first major surface and insulated form one another and connected to said P region and said N region respectively; and

a plurality of contact bumps connected to each of said first and second metallized layers;

said plurality of contact bumps connected to said first metallizing layer being aligned along a first straight row;

said plurality of contact bumps connected to said second metallizing layer being aligned along a second straight row.

13. The device of claim 12 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers;

said first, second and third metallizing layers comprising source, drain and gate electrodes respectively of a MOSgated device.

14. The device of claim 12 and a bottom metallized layer extending across said second major surface.

15. The device of claim 12 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.

16. The device of claim 12 wherein said first and second rows are parallel to one another.

17. The device of claim 12 wherein said silicon wafer is a rectangular wafer having an area defined by a given length and a given width, said length being greater than said width;

said first and second rows of bumps being parallel to one another and being symmetric about a diagonal line across said wafer.

18. The device of claim 17 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers;

said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.

19. The device of claim 14 wherein said silicon wafer is a rectangular wafer having an area defined by a given length and a given width, said length being greater than said width;

said first and second rows of bumps being parallel to one another and being symmetric about a diagonal line across said wafer.

20. The device of claim 12 which further includes a bottom metallized layer extending across said second major surface.

21. A bidirectional conduction flip chip device comprising a silicon wafer having first and second parallel major surfaces;

first and second laterally separated MOSgated devices formed in said silicon wafer;

said first and second MOSgated devices comprising a first and a second source region respectively of one conductivity formed into a first and second spaced lateral area respectively of said first major surface, a first and second channel region respectively of a second conductivity type receiving said first and second source region, respectively a common drain region receiving said first and second channel regions and extending to said second major surface, and a first and second gate structure respectively disposed on said first major surface and operable to invert respective portions of said first and second channel regions to allow conduction from said first and second source regions respectively to said drain region;

first and second laterally spaced source metallized layers disposed atop said first major surface and connected to said first and second source regions respectively; and

first and second laterally spaced gate metallized layers atop said first major surface and connected to said first and second gate structures respectively.

22. The device of claim 21 which further includes at least one contact bump connected to each of said source and gate metallized layers.

23. The device of claim 22 which includes a respective plurality of contact bumps connected to each of said source metallized layers;

each of said plurality of contact bumps arranged in respective spaced rows which are parallel to one another.

24. The device of claim 21 wherein said first and second source regions are disposed in laterally interdigitated relation with respect to one another.

25. The device of claim 23 wherein said first and second source regions are disposed in laterally interdigitated relation with respect to one another.

26. The device of claim 21 which further includes a metal layer on said second major surface.

27. A semiconductor device comprising a silicon die having first and second parallel surfaces;

a region of one conductivity type extending from said first surface and into the body of said die;

a junction pattern defined in said device formed by a plurality of laterally spaced diffusions of the other conductivity type into said region of one conductivity type;

a first conductive electrode formed atop said first surface and in contact with said first plurality of diffusions;

a second conductive electrode formed atop said first surface which is coplanar with and laterally spaced from and insulated from said first conductive electrode and in electrical contact with the body of said die through a high conductivity element; and

at least one solder ball connector formed atop each of said first and second conductive electrodes respectively;

the current path from said first conductive electrode to said second conductive electrode having a vertical component which is generally perpendicular to said first surface.

28. A semiconductor device according to claim 27, wherein said high conductivity element is a sinker diffusion of higher conductivity than said body region.

29. A semiconductor device according to claim 27, wherein said high conductivity element is a metallic material residing in a trench formed in said body of said die.