Low-leakage integrated circuits and dynamic logic circuits

• US 20040021501A1
• Filed: 06/10/2003
• Published: 02/05/2004
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Michigan Regents of The Universit of
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Das, Koushik K., Brown, Richard B.
• Granted Patent: US 6,933,744 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

An integrated circuit is disclosed that includes one or more blocks of switching logic (comprised of transistors) connected between a power supply and a common node. A control transistor connects the common node to ground. The control transistor has a higher threshold voltage level than the voltage threshold level(s) of the transistors that comprise the switching logic blocks. A bias generator provides a positive bias to the body of the control transistor when the control transistor is “on.”

Further disclosed is an integrated circuit comprising a first plurality of serially connected transistors establishing a first current path from a voltage source to ground and a second plurality of serially connected transistors establishing a second current path from the voltage source to ground. The first and second plurality of transistors each includes at least one high-threshold transistor. The integrated circuit further includes a means for decreasing a resistance level of the high threshold transistors when the high threshold transistors are on.

Claims

1. An integrated circuit, comprising:

one or more blocks of switching logic connected between a voltage source and a common node, said switching logic block(s) being comprised of a plurality of transistors having one or more threshold voltage levels;

a control transistor connected between said common node and ground, wherein said control transistor has a threshold voltage level that is greater than said threshold voltage level(s) of said switching logic block transistors; and

a bias generator configured to provide a positive bias to the body of said control transistor when said control transistor is “

on.”

2. The integrated circuit of claim 1, wherein said control transistor is configured to be “

on”

when the integrated circuit is in its “

active mode.”

3. The integrated circuit of claim 1, wherein said bias generator does not provide a positive bias to said control transistor body when said control transistor is “

off.”

4. The integrated circuit of claim 3, wherein said control transistor is configured to be “

off”

when the integrated circuit is in its “

standby mode.”

5. The integrated circuit of claim 1, wherein said threshold voltage level(s) of said switching logic block transistors is below approximately one fourth of said voltage source.

6. The integrated circuit of claim 1, wherein said threshold voltage level of said control transistor is above approximately one third of said voltage source.

11. The integrated circuit of claim 1, wherein said threshold voltage level(s) of said switching logic block transistors is below one fourth of said voltage source.

7. An integrated circuit, comprising:

one or more blocks of switching logic connected between a power supply and a common node, said switching logic block(s) being comprised of a plurality of transistors having one or more threshold voltage level(s);

a first control transistor and a second control transistor connected in series between said common node and ground, wherein said first and second control transistors have threshold voltage levels that are greater than said threshold voltages of said switching logic block transistors; and

a bias generator configured to provide a positive bias to the bodies of each of said first and second control transistors when said control transistors are “

on.”

8. The integrated circuit of claim 7, wherein said first and second control transistors are configured to be “

on”

when the integrated circuit is in its “

active mode.”

9. The integrated circuit of claim 7, wherein said bias generator does not provide a positive bias to the bodies of said first and second control transistors when said control transistors are “

off.”

10. The integrated circuit of claim 9, wherein said control transistors are configured to be “

off”

when the integrated circuit is in its “

standby mode.”

12. The integrated circuit of claim 7, wherein said threshold voltage level(s) of said control transistors is above approximately one third of said voltage source.

13. A method of reducing leakage current in an integrated circuit, comprising:

providing one or more blocks of switching logic, said switching logic block(s) comprising a plurality of transistors having one or more threshold voltage levels;

connecting said switching logic blocks to ground through a control transistor, said control transistor having a threshold voltage level that is greater than said threshold voltage level(s) of said switching logic block transistors; and

providing a positive body bias to said control transistor when said control transistor is “

on”

.

14. The method of claim 13, further comprising the step of configuring said control transistor to be “

on”

when the integrated circuit is in “

active”

mode; and

configuring said control transistor to be “

off”

when the integrated circuit is in “

standby”

mode.

15. A method of operating an integrated circuit, comprising:

providing one or more blocks of switching logic, said switching logic block(s) comprising a plurality of transistors having one or more threshold voltage levels;

connecting said switching logic blocks to ground through at least two control transistors connected in series, said control transistors having threshold voltage levels that are greater than said threshold voltage level(s) of said switching logic block transistors; and

providing a positive body bias to said control transistors when said control transistors are “

on.”

16. The method of claim 15, further comprising the step of configuring said control transistors to be “

on”

when the integrated circuit is in “

active”

mode, and configuring said control transistors to be “

off”

when the integrated circuit is in “

standby”

mode.

17. An integrated circuit, comprising:

a first circuit portion having a plurality of low threshold transistors and a high threshold transistor all serially connected between a supply voltage and ground, said first circuit portion generating a first signal;

a second circuit portion having a low threshold transistor and a high threshold transistor serially connected between a supply voltage and ground, said second circuit generating an output signal in response to said first signal; and

a bias generator connected to the body of at least one of said high threshold transistors, said bias generator configured to provide a positive bias to said at least one high threshold transistor when said at least one high threshold transistor is on.

18. The integrated circuit of claim 17, wherein the integrated circuit is in standby mode when said at least one high threshold transistor is off.

19. The integrated circuit of claim 18, wherein said bias generator is configured not to provide said positive bias to said at least one high threshold transistor when said at least one high threshold transistor is off.

20. The integrated circuit of claim 17, wherein said bias generator is connected to each of said high threshold transistors in said first and second circuit portions.

21. The integrated circuit of claim 17, further comprising a common transistor serially connected to said first circuit portion and serially connected to said second circuit portion, said common transistor providing a current flow path from said first circuit portion to ground, and further providing a current flow path from said second circuit portion to ground.

22. The integrated circuit of claim 21, wherein said common transistor is a high threshold transistor.

23. The integrated circuit of claim 22, wherein a gate of said common transistor is responsive to a control signal, which is independent of a clock signal.

24. The integrated circuit of claim 17, wherein said bias generator is configured to provide positive body biases to both said high threshold transistor in said first circuit portion and said high threshold transistor in said second circuit portion.

25. The integrated circuit of claim 24, wherein said high threshold transistor in said first circuit portion is responsive to a clock signal.

26. The integrated circuit of claim 24, wherein at least one of said transistors in said first circuit portion has a gate that is responsive to an input signal to the circuit, and wherein said high threshold transistor is connected downstream of said input responsive transistor in a current flow path between said supply voltage and ground.

27. The integrated circuit of claim 26, wherein said second circuit portion includes a high threshold transistor and a low threshold transistor, and wherein a drain of said high threshold transistor is connected to a drain of said low threshold transistor.

28. The integrated circuit of claim 24, wherein at least one of said transistors in said first circuit portion has a gate that is responsive to an input signal to the circuit, and wherein said high threshold transistor is connected upstream of said input responsive transistor in a current flow path between said supply voltage and ground.

29. The integrated circuit of claim 28, wherein said second circuit portion includes a high threshold transistor and a low threshold transistor, and wherein a drain of said low threshold transistor is connected to a drain of said high threshold transistor.

30. The integrated circuit of claim 28, wherein said first signal is present at a first node, and wherein said first node is selectively connected to ground through a switch.

31. The integrated circuit of claim 30, wherein said switch is a transistor.

32. A method of operating an integrated circuit, comprising:

serially connecting a first plurality of transistors so as to establish a first current path between a supply voltage and ground, wherein at least one of said transistors is a high threshold transistor; and

applying a positive bias to a body of said high threshold transistor when said transistor is on.

33. The method of claim 32, further comprising the steps of removing said positive bias when said high threshold transistor is off.

34. The method of claim 32, further comprising:

serially connecting a second plurality of transistors so as to establish a second current path between said supply voltage and ground;

providing a signal from said first plurality of transistors to said second plurality of transistors over a common node, said signal being used to drive gates of said second plurality of transistors; and

selectively modifying said signal provided from said first plurality of transistors independently of values of input signals to the circuit.

35. An integrated circuit, comprising:

a first plurality of serially connected transistors establishing a first current path from a supply voltage to ground;

a second plurality of serially connected transistors establishing a second current path from said supply voltage to ground;

wherein said first and second plurality of transistors each includes at least one high-threshold transistor; and

a means for decreasing a resistance level of said high threshold transistors when said high threshold transistors are on.

36. The integrated circuit of claim 35, wherein said means for decreasing a resistance comprises a means for applying a positive body bias to said high threshold transistors.

37. The integrated circuit of claim 35, wherein said first plurality of transistors and said second plurality of transistors are connected such that said first current path and said second current path both flow through a single high threshold transistor.

38. The integrated circuit of claim 35, further comprising a means for selectively turning said second plurality of transistors on and off independent of values of input signals to the circuit.