Phase and amplitude digital modulation circuit and method

• US 20040021523A1
• Filed: 01/09/2003
• Published: 02/05/2004
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: Centre National D'Etudes Spatiales
• Original Assignee: Centre National D'Etudes Spatiales
• Inventors: Sadowy, Jerome, Lalaurie, Jean-Claude, Boulanger, Cyrille, Lapierre, Luc
• Granted Patent: US 6,831,526 B2
• Time in Patent Office: Days
• US Class Current: 332/103
• CPC Class Codes: H03C 7/025 using semiconductor devices
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

The invention concerns a method and a circuit for modulating a carrier signal (Se) with a signal (SCj) comprising at least a modulation cell (CMi) by phase shift for receiving two digital control signals (Scji, SCji2) representing at least part of the digital modulation signal (SCj). For at least a value of the digital modulation signal (SCj), the method consists in applying on at least a common modulation cell (CMi), two digital control signals (SCji1, SCji2) of identical value, said modulation cell (CMi) deliver a signal, called modulated elementary signal (Ssi), which is null for said digital modulation signal value (SCj).

Claims

1. A method for modulating a carrier signal (Se) with a digital modulation signal (SCj), implemented by a modulator circuit (1) comprising at least one modulation cell (CMi) intended to receive two digital control signals (SCji1, SCji2) representing at least a part of the digital modulation signal (SCj), wherein, for at least one value of the digital modulation signal (SCj), two digital control signals (SCji1, SCji2) of equal value are applied to at least one given modulation cell (CMi).

2. The method as claimed in claim 1, wherein at least one modulation cell (CMi) receiving two digital control signals (SCji1, SCji2) of equal value for at least one value of the digital modulation signal (SCj) is designed to deliver a signal, referred to as a modulated elementary signal (Ssi), which is zero for this value of the digital modulation signal (SCj).

3. The method as claimed in one of claims 1 or 2, wherein at least one modulation cell (CMi) is a phase-shift keying modulation cell.

4. The method as claimed in one of claims 1 to 3, wherein at least one modulation cell (CMi) is designed to deliver a modulated elementary signal (Ssi) with two phase states in opposition and a single amplitude state when it receives complementary digital control signals (SCji1, SCji2), and to deliver a modulated elementary signal (Ssi) which is zero when it receives digital control signals (SCji1, SCji2) of equal value.

5. The method as claimed in claim 4, wherein, when the two digital control signals (SCji1, SCji2) are of equal value, they are both equal to 0.

6. The method as claimed in one of claims 1 to 5, wherein the modulator circuit (1) comprises at least two modulation cells (CMi), and wherein, for at least one value of the digital modulation signal (SCj), two digital control signals (SCji1, SCji2) of equal value are applied to at least one modulation cell (CMi) and two digital control signals (SCji1, SCji2) of complementary values are applied to at least one other modulation cell (CMi).

7. The method as claimed in one of claims 1 to 6, wherein, for at least one value of the digital modulation signal (SCj), two digital control signals (SCji1, SCji2) of equal value are applied to at least one modulation cell (CMi), and wherein, for at least one other value of the digital modulation signal (SCj), two digital control signals (SCji1, SCji2) of complementary values are applied to this (these) modulation cell(s) (CMi).

8. The method as claimed in one of claims 1 to 7, wherein an input signal (SDi) coming from the carrier signal (Se) is delivered to each modulation cell (CMi) via impedance matching means (7), which are designed so that the modulation cell (CMi) is at least substantially impedance-matched both when the digital control signals (SCji1, SCji2) that it receives are complementary and when they are equal.

9. The method as claimed in claim 8, wherein the impedance matching means (7) comprise, for each modulation cell (CMi), a transistor (3), which receives the input signal (SDi) and is connected to the modulation cell (CMi), and a parallel resistor (6) between the transistor (3) and ground.

10. The method as claimed in one of claims 1 to 9, wherein a modulator circuit (1) is used with a distributed structure comprising a plurality of derived branches (Bi), each comprising at least one modulation cell (CMi) intended to receive two digital control signals (SCji1, SCji2), each derived branch (Bi) delivering a signal referred to as a modulated branch-output signal (Ssi), and wherein the modulated branch-output signals (Ssi) coming from the various derived branches (Bi) are added in phase in order to form a modulated output signal (Ss).

11. A modulator circuit capable of modulating a carrier signal (Se) with a digital modulation signal (SCj), comprising at least one modulation cell (CMi) intended to receive two digital control signals (SCji1, SCji2) representing at least a part of the digital modulation signal (SCj), wherein it is designed so that, for at least one value of the digital modulation signal (SCj), at least one given modulation cell (CMi) receives two digital control signals (SCji1, SCji2) of equal value.

12. The circuit as claimed in claim 11, wherein at least one modulation cell (CMi) receiving two digital control signals (SCji1, SCji2) of equal value for at least one value of the digital modulation signal (SCj) is designed to deliver a signal, referred to as a modulated elementary signal (Ssi), which is zero for this value of the digital modulation signal (SCj).

13. The circuit as claimed in one of claims 11 or 12, wherein at least one modulation cell (CMi) is a phase-shift keying modulation cell.

14. The circuit as claimed in one of claims 11 to 13, wherein at least one modulation cell (CMi) is designed to deliver a modulated elementary signal (Ssi) with two phase states in opposition and a single amplitude state when it receives complementary digital control signals (SCji1, SCji2), and to deliver a modulated elementary signal (Ssi) which is zero when it receives digital control signals (SCji1, SCji2) of equal value.

15. The circuit as claimed in claim 14, wherein, when the two digital control signals (SCji1, SCji2) are of equal value, they are both equal to 0.

16. The circuit as claimed in one of claims 11 to 15, wherein it comprises at least two modulation cells (CMi), and which circuit is designed so that, for at least one value of the digital modulation signal (SCj), at least one modulation cell (CMi) receives two digital control signals (SCji1, SCji2) of equal value and at least one other modulation cell (CMi) receives two digital control signals (SCji1, SCji2) of complementary values.

17. The circuit as claimed in one of claims 11 to 16, wherein it is designed so that, for at least one value of the digital modulation signal (SCj), at least one modulation cell (CMi) receives two digital control signals (SCji1, SCji2) of equal value, and so that, for at least one other value of the digital modulation signal (SCj), this (these) modulation cell(s) (CMi) receives two digital control signals (SCji1, SCji2) of complementary values.

18. The circuit as claimed in one of claims 11 to 17, wherein it comprises, upstream of each modulation cell (CMi), impedance matching means (7) which supply the modulation cell (CMi) with an input signal (SDi) coming from the carrier signal (Se) and which are designed so that the modulation cell (CMi) is at least substantially impedance-matched both when the digital control signals (SCji1, SCji2) that it receives are complementary and when they are equal.

19. The circuit as claimed in claim 18, wherein the impedance matching means (7) comprise, for each modulation cell (CMi), a transistor (3), which receives the input signal (SDi) and is connected to the modulation cell (CMi), and a parallel resistor (6) between the transistor (3) and ground.

20. The circuit as claimed in one of claims 11 to 19, wherein it has a distributed structure comprising a plurality of derived branches (Bi), each comprising at least one modulation cell (CMi) intended to receive two digital control signals (SCji1, SCji2), each derived branch (Bi) delivering a signal referred to as a modulated branch-output signal (Ssi), and means (12) for adding in phase the modulated branch-output signals (Ssi) coming from the various derived branches (Bi) in order to form a modulated output signal (Ss).