Method and apparatus for saving current in a memory device

• US 20040022116A1
• Filed: 08/01/2002
• Published: 02/05/2004
• Est. Priority Date: 08/01/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Bell, Debra M., Drexler, Adrian J.
• Granted Patent: US 6,834,023 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as during periods of automatic precharge. Because address data need not be provided while the bank is in an automatic precharge mode, the current used to keep the address lines active during this time may be conserved by suitably disabling the address lines for the duration of the automatic precharge. Disabling the various address lines may be accomplished by, for example, interposing a enabling element such as a field effect transistor within the address bus driver circuits leading to each bank, and by providing a suitable control signal to the enabling element to activate and deactivate the address line as needed.

Claims

1. A method of reducing current consumption in a memory device, the method comprising the steps of:

executing an automatic precharge to place the memory device in a precharge mode;

disabling an address signal line in the memory device while the memory device remains in the automatic precharge mode; and

enabling the address signal line when the device is no longer in precharge mode.

2. The method of claim 1, wherein an enable circuit couples the address signal line to a memory bank in the memory device.

3. The method of claim 2 wherein the disabling step comprises providing a control signal to the enable circuit to disable the address signal line.

4. The method of claim 3 wherein the enable circuit comprises a field effect transistor.

5. A method of reducing current consumption in a memory device comprising a plurality of memory banks, each of said memory banks having address lines associated therewith, the method comprising the steps of:

executing an automatic precharge to place a selected one of the memory banks in a precharge mode; and

disabling the address lines associated with the selected memory bank while the selected bank remains in the precharge mode.

6. The method of claim 5 further comprising the step of enabling the address lines associated with the selected memory bank when the bank is no longer in precharge mode.

7. The method of claim 6 wherein another of the plurality of memory banks remains active while the address lines associated with the selected memory bank are disabled.

8. The method of claim 6 wherein the address lines associated with another of the plurality of memory banks remain active while the address lines associated with the selected memory bank are disabled.

9. A memory device communicating with an address bus, the memory device comprising:

a memory bank operatively coupled to the address bus by a plurality of address lines to facilitate storage and retrieval of data in the memory bank;

a controller configured to monitor when the memory bank is in an automatic precharge mode, and to provide a control signal in response thereto; and

a disabling circuit switchably coupling the address lines to the memory bank and receiving the control signal from the controller, wherein the disabling circuit is configured to disable the address lines leading to the memory bank in response to the control signal.

10. The memory device of claim 9 wherein the controller is configured to receive a row address strobe signal, a column address strobe signal, and an automatic precharge signal, and to place the memory bank into the automatic precharge mode in response thereto.

11. A memory device comprising:

a plurality of memory banks;

a plurality of address paths, each of the paths connecting to a corresponding one of the plurality of memory banks; and

a plurality of enabling circuits, each of the enabling circuits disabling an address path to one of the plurality of memory banks when the bank is in an automatic precharge mode.

12. The memory device of claim 11 wherein each of the enabling circuits are further configured to enable the address path to the memory bank when the bank is not in an automatic precharge mode.

13. The memory device of claim 11 further comprising a controller operatively coupled to each of the enabling circuits, wherein the controller is configured to provide a control signal to each of the enabling circuits to switch each enabling circuit between an enabling mode and a disabling mode.

14. The memory device of claim 13 wherein the disabling mode corresponds to a period of automatic precharge for the device.

15. A memory device coupled to an address bus by an address signal line, the memory device comprising:

means for executing an automatic precharge to place the memory device in a precharge mode;

means for disabling the address signal line while the memory device remains in the precharge mode; and

means for enabling the address signal line when the device is no longer in precharge mode.

16. The device of claim 15 wherein the means for executing comprises a means for controlling the memory device.

17. The device of claim 15 wherein the means for controlling is operable to provide a control signal to the means for disabling and the means for enabling.

18. A memory device comprising a plurality of memory banks, each of said memory banks having address lines associated therewith, the memory device comprising:

means for executing an automatic precharge to place a selected one of the memory banks in a precharge mode;

means for disabling the address lines associated with the selected memory bank while the selected bank remains in the precharge mode; and

means for enabling the address signal lines associated with the selected memory bank when the bank is no longer in precharge mode.

19. A computer system comprising:

a processor;

an address bus configured to receive address data from the processor;

a memory in communication with the processor via the address bus, the memory having a plurality of storage addresses; and

a data bus configured to transfer data between the processor and the memory;

wherein the memory comprises;

a memory bank operatively coupled to the address bus by a plurality of address lines to facilitate storage and retrieval of data in the memory bank;

a controller configured to monitor when the memory bank is in an automatic precharge mode, and to provide a control signal in response thereto; and

a disabling circuit switchably coupling the address lines to the memory bank and receiving the control signal from the controller, wherein the disabling circuit is configured to disable the address lines leading to the memory bank in response to the control signal.

20. A computer system comprising:

a processor;

an address bus configured to receive address data from the processor;

a memory in communication with the processor via the address bus, the memory having a plurality of storage addresses; and

a data bus configured to transfer data between the processor and the memory;

wherein the memory comprises;

a plurality of memory banks;

a plurality of address paths, each of the paths coupling a corresponding one of the plurality of memory banks to the address bus; and

a plurality of enabling circuits, each of the enabling circuits disabling an address path to one of the plurality of memory banks when the bank is in an automatic precharge mode.

21. A computer system comprising a processor and a memory communicating via an address bus, wherein the memory comprises:

means for executing an automatic precharge to place a selected one of the memory banks in a precharge mode;

means for disabling address lines coupling the selected memory bank to the address bus while the selected bank remains in the precharge mode; and

means for enabling the address lines associated with the selected memory bank when the bank is no longer in precharge mode.

22. A method of reducing current consumption in a memory device, the method comprising the step of executing an automatic precharge command to place the memory device into a precharge mode and to disable an address signal line while the memory device remains in the precharge mode.

23. The method of claim 22 further comprising enabling the address signal line when the device is no longer in precharge mode.

24. A method of reducing current consumption in a memory device comprising a plurality of memory banks, each of said memory banks having address lines associated therewith, the method comprising the steps of:

executing an automatic precharge to place a selected one of the memory banks in a precharge mode;

disabling the address lines associated with the selected memory bank while the selected bank remains in the precharge mode; and

enabling the address signal lines associated with the selected memory bank when the bank is no longer in precharge mode.

25. The method of claim 24 wherein another of the plurality of memory banks remains active while the address lines associated with the selected memory bank are disabled.

26. The method of claim 24 wherein the address lines associated with another of the plurality of memory banks remain active while the address lines associated with the selected memory bank are disabled.