Selectable-tap equalizer

• US 20040022311A1
• Filed: 07/12/2002
• Published: 02/05/2004
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Stojanovic, Vladimir M., Zerbe, Jared L., Chen, Fred F.
• Granted Patent: US 7,292,629 B2
• Time in Patent Office: Days
• US Class Current: 375/229
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03025 using a two-tap delay line
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0058 detection of error based on equalizer tap values
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Claims

1. An apparatus comprising:

a buffer to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

an equalizing circuit coupled to receive the subset of data values from the select circuit and adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

2. The apparatus of claim 1 further comprising a receiver circuit to receive the data signals transmitted on the signaling path during the first and second time intervals, the receiver circuit being coupled to output the plurality of data values to the buffer.

3. The apparatus of claim 2 wherein the equalizing circuit includes an output driver to output an equalizing signal onto the signaling path to adjust the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval, the equalizing signal having an amplitude according to the subset of data values.

4. The apparatus of claim 2 wherein the second time interval is distinct from and subsequent to the first time interval.

5. The apparatus of claim 2 wherein the receiver circuit includes a preamplifier circuit to generate the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval by amplifying the data signal transmitted on the signaling path during the second time interval.

6. The apparatus of claim 5 wherein the equalizing circuit is coupled to the pre-amplifier circuit to adjust amplification of the signal level within the pre-amplifier circuit in accordance with the subset of data values.

7. The apparatus of claim 2 wherein the receiver circuit includes a sampling circuit to generate the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval by sampling the data signal transmitted on the signaling path during the second time interval.

8. The apparatus of claim 7 wherein the equalizing circuit is coupled to the sampling circuit to adjust the signal level generated by the sampling circuit in accordance with the subset of data values.

9. The apparatus of claim 2 wherein the receiver circuit is adapted to receive additional data signals transmitted on the signaling path during a third time interval, the third time interval being distinct from and occurring between the first and second time intervals.

10. The apparatus of claim 9 wherein the buffer is adapted to store, in addition to the plurality of data values transmitted on the signaling path during the first time interval, data values that correspond to at least a portion of the data signals transmitted during the third time interval.

11. The apparatus of claim 9 wherein the third time interval corresponds to a time required to receive a predetermined number of signals in succession.

12. The apparatus of claim 11 wherein the predetermined number of signals corresponds to a predetermined number of data values for which signal levels are adjusted by a transmit circuit.

13. The apparatus of claim 2 further comprising a first transmitter circuit to output transmit data signals on the signaling path during a third time interval.

14. The apparatus of claim 13 wherein the first transmitter circuit and the receiver circuit are adapted to be coupled to a first end of the signaling path.

15. The apparatus of claim 13 wherein the first transmitter circuit and the receiver circuit form a transceiver circuit coupled to the signaling path.

16. The apparatus of claim 13 wherein data values that correspond to the transmit data signals are also stored in the buffer circuit.

17. The apparatus of claim 16 wherein the buffer circuit comprises a receive buffer and a transmit buffer, the receive buffer being coupled to receive the plurality of data values output by the receiver circuit and the transmit buffer being coupled to receive the data values that correspond to the transmit data signals.

18. The apparatus of claim 17 wherein the select circuit is coupled to the receive buffer and the transmit buffer to select the subset of data values therefrom.

19. The apparatus of claim 13 wherein the first transmit circuit comprises a transmit equalizing circuit to output equalizing signals onto the signal path simultaneously with the transmit data signals.

20. The apparatus of claim 19 further comprising a second transmit circuit to output transmit data signals on another signaling path during the third time interval.

21. The apparatus of claim 20 wherein the transmit equalizing circuit comprises:

a transmit buffer to store a data value that corresponds to a transmit data signal output onto the signaling path by the transmitter circuit;

a multiplexer having a first input coupled to receive the data value from the transmit buffer, and a second input coupled to an input of the second transmit circuit; and

an output driver having an input coupled to an output of the multiplexer, and an output to output the equalizing signals onto the signal path.

22. The apparatus of claim 21 further comprising a configuration circuit having an output coupled to a control input of the multiplexer to select either the data value stored in the transmit buffer or a data value supplied to the input of the second transmit circuit to be provided to the output driver comprised by the transmit equalizing circuit.

23. The apparatus of claim 1 further comprising a first transmit circuit to transmit the data signals transmitted on the signaling path during the first time interval and the data signal transmitted on the signaling path during the second time interval.

24. The apparatus of claim 23 wherein the first transmit circuit comprises a transmit equalizing circuit to output equalizing signals onto the signal path simultaneously with the data signals transmitted on the signaling path by the first transmit circuit.

25. The apparatus of claim 24 further comprising a second transmit circuit to transmit data signals on another signaling path.

26. The apparatus of claim 25 wherein the transmit equalizing circuit comprises:

a transmit buffer to store a data value that corresponds to one of the data signals transmitted on the signaling path by the first transmit circuit;

a multiplexer having a first input coupled to receive the data value from the transmit buffer, and a second input coupled to an input of the second transmit circuit; and

an output driver having an input coupled to an output of the multiplexer, and an output to output the equalizing signals onto the signal path.

27. The apparatus of claim 26 further comprising a configuration circuit having an output coupled to a control input of the multiplexer to select either the data value stored in the transmit buffer or a data value supplied to the input of the second transmit circuit to be provided to the output driver comprised by the transmit equalizing circuit.

28. The apparatus of claim 23 wherein the equalizing circuit includes an output driver coupled in parallel with the first transmit circuit, the equalizing circuit being adapted to transmit an equalizing signal onto the signaling path during the second time interval to adjust the signal level of the data signal transmitted on the signaling path during the second time interval, the equalizing signal having an amplitude according to the subset of data values.

29. The apparatus of claim 1 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least three possible ranges of signal levels.

30. The apparatus of claim 1 wherein each of the data signals transmitted on the signaling path during the first time interval is representative of at least two binary bits of information.

31. The apparatus of claim 1 further comprising a configuration circuit to store the select value and to output the select value to the select circuit, the select value being output to the select signal as a plurality of signals.

32. The apparatus of claim 31 wherein the configuration circuit is adapted to systematically step the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values.

33. The apparatus of claim 32 wherein the configuration circuit is adapted to determine, for each test value in the sequence of test values, a measure of correctly received data values.

34. The apparatus of claim 33 wherein the configuration circuit is further adapted to set the select value according to the test value for which the measure of correctly received data values is highest.

35. The apparatus of claim 31 wherein the configuration circuit is adapted to adjust the select value according to the plurality of data values.

36. The apparatus of claim 31 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of data values and a plurality of weight values that correspond respectively to the subset of data values.

37. The apparatus of claim 36 wherein the configuration circuit is adapted to output the weight values to the equalizing circuit.

38. The apparatus of claim 37 wherein the configuration circuit is adapted to step at least one of the weight values through a sequence of test weight values in a calibration operation.

39. The apparatus of claim 1 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of data values and a plurality of weight values that correspond respectively to the subset of data values.

40. The apparatus of claim 39 further comprising a configuration circuit coupled to output the plurality of weight values to the equalizing circuit.

41. The apparatus of claim 40 wherein the configuration circuit is adapted to step at least one of the plurality of weight values through a sequence of test weight values in a calibration operation.

42. The apparatus of claim 41 wherein the configuration circuit is adapted to determine, for each test weight value in the sequence of test weight values, a measure of correctly received data values.

43. The apparatus of claim 42 wherein the configuration circuit is further adapted to set the at least one of the plurality of weight values according to the test weight value for which the measure of correctly received data values is highest.

44. The apparatus of claim 40 wherein the configuration circuit is adapted to adjust at least one of the plurality of weight values according to the plurality of data values.

45. The apparatus of claim 1 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of data values and a plurality of polarity values that correspond respectively to the subset of data values, each polarity value indicating whether a corresponding data value within the subset of data values shall make a positive or negative contribution to the signal level.

46. A receiver circuit to receive data signals transmitted on a signaling path, the receiver circuit comprising:

a buffer to store a plurality of data values that correspond to data signals transmitted on the signaling path during a first time interval; and

an equalizing circuit coupled to receive a subset of the plurality of data values from the buffer circuit and adapted to adjust, according to the subset of the plurality of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval, the second time interval being offset from the first time interval by a third time interval.

47. The receiver circuit of claim 46 wherein the third time interval corresponds to a length of time during which a data value that corresponds to a data signal transmitted on the signaling path by a transmit circuit is used within the transmit circuit to generate an equalization signal.

48. The receiver circuit of claim 46 wherein the third time interval is determined according to a programmable configuration value.

49. The receiver circuit of claim 46 comprising a configuration circuit store a timing value indicative of the third time interval.

50. The receiver circuit of claim 49 wherein the configuration circuit is adapted to systematically step the timing value through a sequence of test values to determine a setting of the timing value.

51. The receiver circuit of claim 50 wherein the configuration circuit is adapted to determine, for each test value in the sequence of test values, a measure of correctly received data values.

52. The receiver circuit of claim 51 wherein the configuration circuit is further adapted to set the timing value according to the test value for which the measure of correctly received data values is highest.

53. The receiver circuit of claim 46 further comprising a select circuit coupled to the buffer and the equalizing circuit, the select circuit being adapted to select the subset of the plurality of data values according to a select value and to output the subset of the plurality of data values to the equalizing circuit.

54. The receiver circuit of claim 53 wherein the plurality of data values includes M data values and the subset of the plurality of data values selected by the select circuit includes N data values, M being greater than N.

55. The receiver circuit of claim 53 further comprising a configuration circuit to store the select value and to output the select value to the select circuit, the select value being output to the select signal as a plurality of signals.

56. The receiver circuit of claim 55 wherein the configuration circuit is adapted to systematically step the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of the plurality of data values.

57. The receiver circuit of claim 56 wherein the configuration circuit is adapted to determine, for each test value in the sequence of test values, a measure of correctly received data values.

58. The receiver circuit of claim 57 wherein the configuration circuit is further adapted to set the select value according to the test value for which the measure of correctly received data values is highest.

59. The receiver circuit of claim 46 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of the plurality of data values and a plurality of weight values that correspond respectively to the subset of the plurality of data values.

60. The receiver circuit of claim 59 wherein a configuration circuit is coupled to output the plurality of weight values to the equalizing circuit.

61. The receiver circuit of claim 60 wherein the configuration circuit is adapted to step at least one of the plurality of weight values through a sequence of test weight values in a calibration operation.

62. The receiver circuit of claim 61 wherein the configuration circuit is adapted to determine, for each test weight value in the sequence of test weight values, a measure of correctly received data values.

63. The receiver circuit of claim 62 wherein the configuration circuit is further adapted to set the at least one of the plurality of weight values according to the test weight value for which the measure of correctly received data values is highest.

64. The receiver circuit of claim 46 wherein the equalizing circuit includes an output driver to output an equalizing signal onto the signaling path during the second time interval to adjust the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval, the equalizing signal having an amplitude according to the subset of the plurality of data values.

65. The receiver circuit of claim 46 further comprising a preamplifier circuit to amplify the data signal transmitted on the signaling path during the second time interval and thereby to generate the signal level that corresponds to the data signal.

66. The receiver circuit of claim 65 wherein the equalizing circuit is coupled to the pre- amplifier circuit to adjust amplification of the signal level within the pre-amplifier circuit in accordance with the subset of the plurality of data values.

67. The receiver circuit of claim 46 further comprising a sampling circuit to generate the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval by sampling the data signal transmitted on the signaling path during the second time interval.

68. The receiver circuit of claim 46 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least three possible ranges of signal levels.

69. The receiver circuit of claim 46 wherein each of the data signals transmitted on the signaling path during the first time interval is representative of at least two binary bits of information.

70. The receiver circuit of claim 46 wherein the equalizing circuit is adapted to adjust the signal level in accordance with the subset of the plurality of data values and a corresponding plurality of polarity values, each polarity value indicating whether a corresponding data value within the subset of the plurality of data values shall make a positive or negative contribution to the signal level.

71. A signaling system comprising:

a signaling path;

a transmit circuit coupled to the signaling path to transmit a first data signal thereon during a first transmit interval, the transmit circuit including a transmit equalization circuit coupled to the signal path to transmit a first equalization signal thereon during the first transmit interval, the first equalization signal having a signal level according to data signals transmitted on the signaling path by the transmit circuit during a first time interval that precedes the first transmit interval; and

a receive circuit coupled to the signaling path to receive the first data signal during a first receive interval, the receive circuit including a receive equalization circuit coupled to the signal path to transmit a second equalization signal thereon during the first receive interval, the second equalization signal having a signal level according to data signals received via the signaling path during a second time interval that precedes the first receive interval by an amount of time according to the first time interval.

72. The system of claim 71 wherein the receive equalization circuit comprises:

a buffer to store a plurality of data values that correspond to the data signals received via the signaling path during the second time interval;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

an output driver to output the second equalization signal onto the signaling path, the second equalization signal having an amplitude according to the subset of data values.

73. The system of claim 72 further comprising a configuration circuit to store the select value and to output the select value to the select circuit.

74. The system of claim 73 wherein the configuration circuit is adapted to systematically step the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values.

75. The system of claim 74 wherein the configuration circuit is adapted to determine, for each test value in the sequence of test values, a measure of correctly received data values.

76. The system of claim 75 wherein the configuration circuit is further adapted to set the select value according to the test value for which the measure of correctly received data values is highest.

77. The system of claim 73 wherein the configuration circuit is adapted to adjust the select value according to the plurality of data signals received during the second time interval.

78. The system of claim 71 wherein the transmit equalization circuit comprises:

a buffer to store a plurality of data values that correspond to the data signals transmitted on the signaling path during the first time interval;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

an output driver to output the first equalization signal onto the signaling path, the first equalization signal having an amplitude according to the subset of data values.

79. The system of claim 78 further comprising a configuration circuit to store the select value and to output the select value to the select circuit.

80. The system of claim 79 wherein the configuration circuit is adapted to systematically step the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values.

81. The system of claim 80 wherein the configuration circuit is adapted to determine, for each test value in the sequence of test values, a measure of correctly received data values.

82. The system of claim 81 wherein the configuration circuit is further adapted to set the select value according to the test value for which the measure of correctly received data values is highest.

83. The system of claim 79 wherein the configuration circuit is adapted to adjust the select value according to the plurality of data signals transmitted during the first time interval.

84. The system of claim 71 wherein the first data signal has a signal level that falls within one of at least three possible ranges of signal levels.

85. The system of claim 71 wherein the first data signal is representative of at least two binary bits of information.

86. The system of claim 71 wherein the receive equalization circuit is adapted to adjust the signal level in accordance with the data signals received during the second time interval and a plurality of weight values that correspond respectively to the data signals received during the second time interval.

87. The system of claim 86 wherein the receive circuit further includes a configuration circuit coupled to the receive equalization circuit to output the plurality of weight values thereto.

88. The system of claim 87 wherein the configuration circuit is adapted to step at least one of the plurality of weight values through a sequence of test weight values in a calibration operation.

89. The system of claim 88 wherein the configuration circuit is adapted to determine, for each test weight value in the sequence of test weight values, a measure of correctly received data values.

90. The system of claim 89 wherein the configuration circuit is further adapted to set the at least one of the plurality of weight values according to the test weight value for which the measure of correctly received data values is highest.

91. The system of claim 87 wherein the configuration circuit is adapted to adjust at least one of the plurality of weight values according to the plurality of data signals received during the second time interval.

92. The system of claim 71 wherein the transmit equalization circuit is adapted to adjust the signal level in accordance with the data signals transmitted during the first time interval and a plurality of weight values that correspond respectively to the data signals transmitted during the first time interval.

93. The system of claim 92 wherein the transmit circuit further includes a configuration circuit coupled to the transmit equalization circuit to output the plurality of weight values thereto.

94. The system of claim 93 wherein the configuration circuit is adapted to step at least one of the plurality of weight values through a sequence of test weight values in a calibration operation.

95. The system of claim 94 wherein the configuration circuit is adapted to determine, for each test weight value in the sequence of test weight values, a measure of correctly received data values.

96. The system of claim 95 wherein the configuration circuit is further adapted to set the at least one of the plurality of weight values according to the test weight value for which the measure of correctly received data values is highest.

97. The system of claim 71 wherein the receive equalization circuit is adapted to adjust the signal level of the second equalization signal in accordance with the data signals received during the second time interval and a plurality of polarity values that correspond respectively to the data signals received during the second time interval, each polarity value indicating whether a corresponding one of data signals received during the second time interval shall make a positive or negative contribution to the signal level of the second equalization signal.

98. A method of operation within an integrated circuit device, the method comprising:

storing a plurality of data values, the plurality of data values corresponding to data signals transmitted on a signaling path during a first time interval;

selecting a subset of data values from the plurality of data values; and

adjusting a signal level according to the subset of data values, the signal level corresponding to a data signal transmitted on the signaling path during a second time interval.

99. The method of claim 98 wherein adjusting a signal level according to the subset of data values comprises outputting an equalizing signal onto the signaling path to adjust the signal level, the equalizing signal having an amplitude according to the subset of data values.

100. The method of claim 98 wherein adjusting the signal level comprises adjusting amplification of the signal level according to the subset of data values.

101. The method of claim 100 wherein adjusting amplification of the signal level comprises adjusting amplification of the signal level within a preamplifier circuit.

102. The method of claim 100 wherein adjusting amplification of the signal level comprises adjusting amplification of the signal level within a sampling circuit.

103. The method of claim 98 further comprising transmitting the data signals transmitted on the signaling path during the first time interval.

104. The method of claim 98 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least three possible ranges of signal levels.

105. The method of claim 98 wherein each of the data signals transmitted on the signaling path during the first time interval is representative of at least two binary bits of information.

106. The method of claim 98 further comprising storing the select value in a configuration circuit.

107. The method of claim 98 further comprising systematically stepping the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values.

108. The method of claim 107 wherein systematically stepping the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values comprises:

determining, for each test value in the sequence of test values, a measure of correctly received data values; and

setting the select value according to the test value for which the measure of correctly received data values is highest.

109. A method of operating a receiver circuit, the method comprising:

storing a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval; and

adjusting, according to the subset of the plurality of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval, the second time interval being offset from the first time interval by a third time interval.

110. The method of claim 109 wherein the third time interval corresponds to a length of time during which a data value that corresponds to a data signal transmitted on the signaling path by a transmit circuit is used within the transmit circuit to generate an equalization signal.

111. The method of claim 109 further comprising storing, in a configuration circuit, a timing value indicative of the third time interval.

112. The method of claim 109 further comprising selecting the subset of the plurality of data values according to a select value.

113. The method of claim 112 further comprising storing the select value in a configuration circuit.

114. The method of claim 112 further comprising systematically stepping the select value through a sequence of test values to determine a setting of the select value that corresponds to the plurality of data values.

115. The method of claim 109 wherein adjusting the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval comprises outputting an equalizing signal onto the signaling path during the second time interval to adjust the signal level, the equalizing signal having an amplitude according to the subset of the plurality of data values.

116. The method of claim 109 wherein adjusting the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval comprises adjusting amplification of the signal level within a pre-amplifier circuit in accordance with the subset of the plurality of data values.

117. The method of claim 109 wherein adjusting the signal level that corresponds to the data signal transmitted on the signaling path during the second time interval comprises adjusting amplification of the signal level within a sampling circuit in accordance with the subset of the plurality of data values.

118. The method of claim 109 wherein each of the data signals transmitted on the signaling path during the first time interval has a signal level that falls within one of at least three possible ranges of signal levels.

119. The method of claim 109 wherein each of the data signals transmitted on the signaling path during the first time interval is representative of at least two binary bits of information.

120. A method of operating a signaling system, the method comprising:

transmitting a first data signal on a signaling path during a first transmit interval;

transmitting a first equalization signal on the signal path during the first transmit interval, the first equalization signal having a signal level according to data signals transmitted on the signaling path during a first time interval that precedes the first transmit interval;

receiving the first data signal from the signaling path during a first receive interval; and

transmitting a second equalization signal on the signal path during the first receive interval, the second equalization signal having a signal level according to data signals received from the signaling path during a second time interval that precedes the first receive interval by an amount of time according to the first time interval.

121. The method of claim 120 wherein transmitting a second equalization signal on the signal path during the first time interval comprises:

storing a plurality of data values that correspond to the data signals received from the signaling path during the second time interval;

selecting a subset of data values from the plurality of data values according to a select value; and

outputting the second equalization signal onto the signaling path, the second equalization signal having an amplitude according to the subset of data values.

122. The method of claim 121 further comprising storing the select value in a configuration circuit.

123. The method of claim 122 further comprising systematically stepping the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values.

124. The method of claim 123 wherein systematically stepping the select value through a sequence of test values to determine a setting of the select value that corresponds to the subset of data values comprises:

determining, for each test value in the sequence of test values, a measure of correctly received data values; and

setting the select value according to the test value for which the measure of correctly received data values is highest.

125. The method of claim 120 wherein transmitting a first equalization signal on the signal path during the first transmit interval comprises:

storing a plurality of data values that correspond to the data signals transmitted on the signaling path during the first time interval;

selecting a subset of data values from the plurality of data values according to a select value; and

outputting the first equalization signal onto the signaling path, the first equalization signal having an amplitude according to the subset of data values.

126. The method of claim 120 wherein the first data signal has a signal level that falls within one of at least three possible ranges of signal levels.

127. The method of claim 120 wherein the first data signal is representative of at least two binary bits of information.