Method for testing chip configuration settings

• US 20040024556A1
• Filed: 07/01/2003
• Published: 02/05/2004
• Est. Priority Date: 07/24/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Wang, Jing-Rung
• Granted Patent: US 7,210,080 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]

Abstract

The present invention relates to a method for testing a chip, particularly to a method for testing chip configuration settings, essentially installing the chip on a main board after the chip fabrication is finished. The test comprises starting power first of all, a power on self test being performed by the system; loading a BIOS program, wherein the BIOS program includes a configuration test process; testing the configuration settings of the chip by the configuration test process; inputting test data in turn; then enabling registers corresponding to the chip configuration space depending on the test data, for starting the chip operation; obtaining the data, produced by the chip operation, to be compared with an expected result, in order for performing the verification of chip configuration settings at the final stage before the actual chip operation is started, so as to speed the development and modification for the chip.

Claims

1. A method for testing chip configuration settings, comprising the steps of:

providing a main board including a chip to be tested therein;

providing a BIOS program including a configuration test process therein;

starting power;

performing a power on self test;

loading said BIOS program; and

testing the configuration settings in a configuration space of said chip.

2. The method according to claim 1, wherein said configuration test process included in said BIOS program comprising the steps of:

providing a test datum;

providing an expected result datum corresponding to said test datum;

inputting said test datum;

enabling a register corresponding to said chip configuration space depending on said test datum;

obtaining a result datum after operating of said chip; and

comparing said obtained result datum with said expected result datum.

3. The method according to claim 2, further comprising a step of recording said comparison result.

4. The method according to claim 3, further comprising a step of generating a difference report.

5. The method according to claim 1, wherein said configuration test process included in said BIOS program comprising the steps of:

providing at least one sets of test data;

providing at least one sets of expected result data corresponding to said test data;

inputting said test data;

enabling a register corresponding to said chip configuration space depending on said test data;

obtaining corresponding result data after operating of said chip in accordance with said test data; and

comparing said obtained result data with said corresponding expected result data.

6. The method according to claim 5, wherein said test data are implemented in the form of a data table list.

7. The method according to claim 5, wherein said expected result data are implemented in the form of a data table list.

8. The method according to claim 5, further comprising a step of recording said comparison results.

9. The method according to claim 8, wherein said records of comparison results are implemented in the form of a data table list.

10. The method according to claim 9, wherein each of said records of comparison results includes a result and difference obtained from said comparison.

11. The method according to claim 5, further comprising a step of generating a test report.

12. The method according to claim 10, further comprising a step of generating a difference report.