Computer system implementing synchronized broadcast using timestamps

• US 20040024925A1
• Filed: 06/30/2003
• Published: 02/05/2004
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Cypher, Robert E., Wood, David A., Wicki, Thomas M., Hill, Mark D.
• Granted Patent: US 7,366,843 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.

Claims

1. A device comprising:

a cache;

an address-in buffer configured to store an address packet;

a data-in buffer configured to store a data packet, wherein the data-in buffer is configured to store a timestamp corresponding to the data packet;

a controller coupled to the data-in buffer and con figured to inhibit receipt of the data packet from the data-in buffer based on a value of the timestamp;

wherein an access right to a first coherency unit cached in the cache transitions in response to receipt of the data packet from the data-in buffer;

wherein an ownership responsibility for the first coherency unit in the cache transitions in response to receipt of the address packet from the address-in buffer.

2. The device of claim 1, further comprising a counter configured to increment in response to receipt of the address packet from the address-in buffer.

3. The device of claim 2, wherein the controller is configured to inhibit receipt of the data packet if the value of the timestamp is greater than a current count of the counter.

4. The device of claim 1, wherein the address-in buffer is configured to store an address timestamp corresponding to the address packet.

5. The device of claim 4, wherein the controller is configured to inhibit receipt of the data packet if the value of the timestamp corresponding to the data packet is greater than a value of the address timestamp.

6. A computer system comprising:

a system memory;

a first active device configured to access data stored in the system memory, wherein the first active device includes a first cache configured to store data accessed by the first active device;

an address network for conveying address packets between the first active device and the system memory;

a data network for conveying data packets between the first active device and the system memory;

wherein an access right corresponding to a given block allocated in the first cache transitions in response to a corresponding data packet being received by the first cache;

wherein an ownership responsibility for the given block allocated in the first cache transitions in response to a corresponding address packet being received by the first cache, wherein the access right transitions at a different time than the ownership responsibility transitions;

wherein the first cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.

7. The computer system as recited in claim 6, wherein the first active device includes a data-in buffer configured to store the corresponding data packet and the timestamp, an address-in buffer configured to store the corresponding address packet, and a counter configured to increment when the corresponding address packet is received by the first cache from the address-in buffer, wherein the first cache is configured to inhibit receipt of the corresponding data packet from the data-in buffer if a current value of the counter is less than the value of the timestamp.

8. The computer system as recited in claim 6, wherein the first active device includes a data-in buffer configured to store the corresponding data packet and the timestamp, an address-in buffer configured to store the corresponding address packet and an address timestamp associated with the corresponding address packet, wherein the first cache is configured to receive the corresponding address packet from the address-in buffer, wherein the first cache is configured to inhibit receipt of the corresponding data packet from the data-in buffer if a value of the address timestamp is less than the value of the timestamp.

9. The computer system as recited in claim 8, wherein the address network is configured to assign the address timestamp to the corresponding address packet.

10. The computer system as recited in claim 6, further comprising a second active device including a second cache, wherein the second active device is configured to assign the timestamp to the corresponding data packet and to send the timestamp and the corresponding data packet on the data network to the first active device.

11. The computer system as recited in claim 10, wherein the value of the timestamp is equal to a value of a counter included in the second active device at a time when the second active device sent the corresponding data packet, wherein the counter is configured to increment each time the second active device receives an address packet.

12. The computer system as recited in claim 10, wherein the value of the timestamp is equal to an address timestamp of a most-recently received address packet received by the second active device.

13. The computer system as recited in claim 6, further comprising a second active device including a second cache, wherein an access right corresponding to another block allocated in the second cache transitions in response to another corresponding data packet being received by the second cache through the data network.

14. The computer system as recited in claim 7, wherein the corresponding address packet is a read-to-own packet.

15. The computer system as recited in claim 8, wherein the corresponding data packet received by the first cache is conveyed through the data network from the second active device in response to the read-to-own packet.

16. The computer system as recited in claim 9, wherein an access right of a block allocated in the second cache that corresponds to the read-to-own packet transitions in response to the second active device sending the corresponding data packet.

17. The computer system as recited in claim 9, wherein an ownership state corresponding to the block allocated in the second cache that corresponds to the read-to-own packet transitions in response to the second cache receiving the read-to-own packet.

18. The computer system as recited in claim 8, further comprising a third active device including a third cache, wherein an access right of a corresponding block allocated in the third cache transitions from a read access night to an invalid access night in response to the read-to-own packet being received by the third cache through the address network.

19. The computer system as recited in claim 6, wherein the corresponding data packet is provided to the first cache through the data network in response to a write stream packet sent by the first active device, and wherein the corresponding data packet is sent by a previous owner of a cache block corresponding to the write stream packet.

20. The computer system as recited in claim 13, wherein the corresponding data packet is an encoded acknowledgment that excludes data corresponding to the cache block.

21. A method for maintaining coherency in a. computer system comprising:

a first active device storing a first address packet in an address-in buffer;

the first active device storing a first data packet and a corresponding timestamp in data-in buffer;

an access right to a block cached in a first cache included in the first active device transitioning in response to the first cache receiving the first data packet from the data-in buffer;

an ownership responsibility to the block cached in the first cache transitioning in response to the first cache receiving the first address packet from the address-in buffer, wherein the access right transitions at a different time than the ownership responsibility transitions;

the first cache inhibiting receipt of the first data packet based on a value of the corresponding timestamp.

22. The method of claim 21, further comprising a counter incrementing in response to the first cache receiving the first address packet from the address-in buffer, wherein said inhibiting receipt comprises inhibiting receipt of the first data packet if the value of the corresponding timestamp is greater than a current value of the counter.

23. The method of claim 21, wherein said storing a first address packet in the address-in buffer includes storing an address timestamp corresponding to the first address packet in the address-in buffer.

24. The method of claim 23, wherein said inhibiting receipt comprises inhibiting receipt of the first data packet if the value of the corresponding timestamp is greater than a value of the address timestamp.

28. The method of claim 25, further comprising an address network assigning the address timestamp to the first address packet.

25. The method of claim 21, further comprising a second active device assigning the corresponding timestamp to the first data packet and sending the corresponding timestamp and the first data packet to the first active device on a data network.

26. The method of claim 25, wherein said assigning comprises the second active device assigning the corresponding timestamp equal to a value of a counter included in the second active device, wherein the counter increments each time an address packet is received by a second cache included in the second active device.

27. The method of claim 25, wherein said assigning comprises the second active device assigning the corresponding timestamp equal to an address timestamp of an address packet most-recently received by a second cache included in the second active device.