Generic bridge core

• US 20040024943A1
• Filed: 07/30/2002
• Published: 02/05/2004
• Est. Priority Date: 07/30/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Paylovsky, Dimitry, Lupien, Gordon F. Jr., Maslyn, David C. Jr.
• Granted Patent: US 6,996,659 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/404 with address mapping

Abstract

An apparatus comprising a plurality of first circuits and a second circuit. Each of the first circuits may be configured to translate attributes and data between one of a plurality of first predetermined formats and a second predetermined format. The second circuit may be configured to route the attributes and data in the second predetermined format from one of the first circuits to another of the first circuits.

Claims

1. An apparatus comprising:

a plurality of first circuits each configured to translate attributes and data between one of a plurality of first predetermined formats and a second predetermined format; and

a second circuit configured to route said attributes and data in said second predetermined format from one of said first circuits to another of said first circuits.

2. The apparatus according to claim 1, wherein each of said first circuits comprises a master sequencer and a slave sequencer.

3. The apparatus according to claim 1, wherein each of said first circuits is coupled between a bus and said second circuit.

4. The apparatus according to claim 1, wherein said second circuit comprises a logic circuit and a plurality of FIFO memories.

5. The apparatus according to claim 4, wherein said logic circuit comprises a plurality of registers, a routing manager, a free buffer manager and a plurality of data buffers.

6. The apparatus according to claim 4, wherein said logic circuit is configured to receive attribute entries from each of said sequencer circuits via a first FIFO memory and present attribute entries to each of said sequencer circuits via a second FIFO memory.

7. The apparatus according to claim 5, wherein said routing manager is configured to select between a plurality of first FIFO memories and a plurality of second FIFO memories.

8. The apparatus according to claim 5, wherein said routing manager comprises two or more clock domain crossing circuits.

9. The apparatus according to claim 1, wherein said apparatus is configured to bridge a plurality of busses.

10. The apparatus according to claim 9, wherein said second circuit operates independently of a clock domain of said busses.

11. The apparatus according to claim 1, wherein said second circuit is configured to route said attributes and data according to a predetermined set of routing rules.

12. The apparatus according to claim 11, wherein said predetermined set of routing rules is programmable.

13. The apparatus according to claim 12, wherein said routing rules are programmable during operation of said apparatus.

14. The apparatus according to claim 11, wherein said apparatus implements a plurality of programmable parameters selected from the group consisting of FIFO depths, routing rules, and arbitration rules.

15. An apparatus comprising:

means for translating attributes and data between a format of each of a plurality of busses and a predetermined format; and

means for routing said translated attributes and data from one bus to another bus.

16. A method for bridging two or more busses comprising the steps of:

translating attributes and data from a format of a first bus into a predetermined format;

translating attributes and data from said predetermined format into a format of a second bus; and

routing said attributes and data in said predetermined format between said first and second busses.

17. The method according to claim 16, further comprising:

remapping address and command attributes from said first bus to said second bus.

18. The method according to claim 16, further comprising:

splitting a transaction when said transaction is not immediately executable.