Methods and systems for performing dynamic power management via frequency and voltage scaling

• US 20040025069A1
• Filed: 06/13/2003
• Published: 02/05/2004
• Est. Priority Date: 08/01/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cyran, Robert J., Gary, Scott P., Sarathy, Vijaya B.P.
• Granted Patent: US 7,155,617 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems are provided for dynamically managing the power consumption of a digital system. These methods and systems broadly provide for varying the frequency and voltage of one or more clocks of a digital system upon request by an entity of the digital system. An entity may request that the frequency of a clock of the processor of the digital system be changed. After the frequency is changed, the voltage point of the voltage regulator of the digital system is automatically changed to the lowest voltage point required for the new frequency if there is a single clock on the processor. If the processor is comprised of multiple processing cores with associated clocks, the frequency is changed to the lowest voltage point required by all frequencies of all clocks.

Claims

1. A method for dynamically managing the power consumption of a digital system comprising the steps of:

accepting clock configuration data comprising a plurality of frequency values for a clock of a processor of the digital system;

accepting voltage configuration data comprising a plurality of voltage points of a voltage regulator and an associated maximum frequency for each voltage point of the plurality of voltage points;

determining a plurality of setpoints for the processor from the clock configuration data and the voltage configuration data wherein the number of setpoints corresponds to the number of frequency values in the plurality of frequency values and each setpoint comprises a frequency value of the plurality of frequency values and a minimum voltage point required for the frequency value;

accepting a request from an entity of the digital system to change a current setpoint of the processor to a new setpoint; and

changing the current setpoint of the processor to the new setpoint wherein a current frequency of the clock is changed to the frequency value of the setpoint and a voltage of the voltage regulator is changed to the voltage point of the setpoint.

2. The method of claim 1 further comprising the steps of:

calling a first function specified by the entity prior to the step of changing the current setpoint if the entity requests that the first function be called; and

calling a second function specified by the entity after the step of changing the current setpoint if the entity requests that the second function be called.

3. The method of claim 1 wherein the clock configuration data and the voltage configuration data are received from a user configurable source.

4. A method for dynamically managing the power consumption of a digital system wherein a processor of the digital system is comprised of a plurality of processing cores wherein each processing core of the plurality of processing cores has an associated clock comprising the steps of:

accepting clock configuration data comprising a plurality of frequency values for each clock of the processor;

accepting voltage configuration data comprising a plurality of voltage points of a voltage regulator and an associated maximum frequency value for each voltage point of the plurality of voltage points;

determining a plurality of setpoints for each processing core of the plurality of processing cores from the plurality of frequency values and the voltage configuration data wherein the number of setpoints for each processing core corresponds to the number of frequency values in the plurality of frequency values of the associated clock of the processing core and each setpoint comprises a frequency value of the plurality of frequency values of the associated clock and a minimum voltage point required for the frequency value;

accepting a request from an entity of the digital system to change a first current setpoint of a first processing core to a first new setpoint; and

changing the first current setpoint of the first processing core to the first new setpoint wherein a current frequency of the associated clock is changed to the frequency value of the first new setpoint and a voltage of the voltage regulator is changed to the voltage point of the first new setpoint if the voltage point of the first new setpoint is the minimum voltage required for all current frequencies of all clocks of the plurality of processing cores.

5. The method of claim 4 wherein

the step of accepting a request further comprises accepting a request from an entity of the digital system to change a first current setpoint of a first processing core to a first new setpoint and at least a second current setpoint of a second processing core to a second new setpoint;

and

the step of changing the first current setpoint comprises changing the first current setpoint of the first processing core to the first new setpoint wherein a current frequency of the associated clock is changed to the frequency value of the first new setpoint and at least changing the second current setpoint of the second processing core to the second new setpoint wherein a current frequency of the associated clock is changed to the frequency value of the second new setpoint and wherein a voltage of the voltage regulator is changed to the voltage point of the first new setpoint or the voltage point of the second new setpoint if either voltage point is the minimum voltage required for all current frequencies of all clocks of the plurality of processing cores.

6. The method of claim 5 further comprising the steps of:

calling a first function specified by the entity prior to the step of changing the first current setpoint if the entity requests that the first function be called; and

calling a second function specified by the entity after the step of changing the first current setpoint if the entity requests that the second function be called.

7. The method of claim 5 wherein the clock configuration data and the voltage configuration data are received from a user configurable source.

8. A method for dynamically managing the power consumption of a digital system comprising the steps of:

accepting a request from an entity of the digital system to change a current frequency of a clock of a processor in the digital system to a new frequency;

changing the current frequency to the new frequency; and

changing automatically a voltage of a voltage regulator of the digital system to the minimum voltage required for the new frequency.

9. The method of claim 8

wherein the processor is comprised of a plurality of processing cores wherein each processing core of the plurality of processing cores has an associated clock;

and

the step of changing automatically a voltage comprises changing automatically a voltage of a voltage regulator of the digital system to the minimum voltage required for all frequencies of all clocks of the processor.

10. The method of claim 9 wherein

the step of accepting a request comprises accepting a request from an entity of the digital system to change at least a first current frequency of a first clock of the processor to a first new frequency and a second current frequency of a second clock of the processor to a second new frequency;

and

the step of changing the current frequency comprises changing at least the first current frequency to the first new frequency and the second current frequency to the second new frequency.

11. A digital system operable to dynamically manage power consumption, the digital system comprising:

a processor;

a voltage regulator connected to regulate voltage of the processor;

a memory coupled to the processor, wherein the memory stores a power scaling library wherein the power scaling library is executable to enable any entity of a plurality of entities of the digital system to cause a current frequency of a clock of the processor to be changed to a new frequency and wherein the power scaling library automatically changes a voltage of the voltage regulator to a minimum voltage required by the new frequency after the current frequency is changed to the new frequency.

12. The system of claim 11 wherein the power scaling library is further executable to enable an entity of the plurality of entities to cause an entity-specified function to be called before the current frequency of the clock is changed to the new frequency and to cause an entity-specified function to be called after the current frequency of the clock is changed to the new frequency.

13. The system of claim 12 wherein the power scaling library is further executable to enable the plurality of entities to obtain a current frequency of the clock, to obtain a current voltage of the voltage regulator, to obtain all valid frequencies of the clock, to obtain a minimum required voltage for each of the valid frequencies of the clock, and to obtain a maximum latency for a change from a first frequency and voltage to a second frequency and voltage.

14. The system of claim 11 wherein

the processor comprises a plurality of processing cores wherein each processing core has an associated clock;

and

the power scaling library is further executable to enable any entity of a plurality of entities of the digital system to cause current frequencies of two or more clocks of the processor to be changed to new frequencies and wherein the power scaling library automatically changes a voltage of the voltage regulator to a minimum voltage required by all frequencies of all clocks after the current frequencies are changed to the new frequencies.

15. The system of claim 14 wherein the power scaling library is further executable to enable an entity of the plurality of entities to cause an entity-specified function to be called before the current frequencies are changed to the new frequencies and to cause an entity-specified function to be called after the current frequencies of the clocks are changed to the new frequencies.

16. The system of claim 15 wherein the power scaling library is further executable to enable the plurality of entities to obtain current frequencies of one or more clocks, to obtain a current voltage of the voltage regulator, to obtain all valid frequencies of one or more clocks, to obtain a minimum required voltage for each of the valid frequencies of one or more clocks, and to obtain a maximum latency for a change from a first frequency and voltage of a clock to a second frequency and voltage of the clock.