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Method for improving instruction selection efficiency in a DSP/RISC compiler

  • US 20040025151A1
  • Filed: 07/31/2002
  • Published: 02/05/2004
  • Est. Priority Date: 07/31/2002
  • Status: Abandoned Application
First Claim
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1. A method for improving instruction selection efficiency in a DSP/RISC compiler, comprising the steps of:

  • determining a semantic tree for a basic block;

    finding all matching combinations for the semantic tree with reference to a set of patterns;

    determining cycle number and instruction length for all combinations;

    filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length; and

    choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination to be the desired object code.

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