Hardware task manager

• US 20040025159A1
• Filed: 05/21/2003
• Published: 02/05/2004
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Scheuermann, W. James, Hogenauer, Eugene B.
• Granted Patent: US 7,653,710 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

Claims

1. An apparatus for coordinating buffer use among tasks in a processing system, wherein the processing system includes a plurality of hardware nodes, wherein a task is executed on one or more of the hardware nodes, wherein a consuming task uses input buffers to obtain data and wherein a producing task uses output buffers to provide data, the apparatus comprising

a task manager for indicating the status of the buffers, the task manager including

an output buffer available indicator associated with an output buffer;

an input buffer available indicator associated with an input buffer; and

a status indicator for indicating that a task is ready to run based on a combination of the output buffer available indicator and the input buffer available indicator.

2. The apparatus of claim 1, further comprising

wherein the output buffer available indicator includes using an output buffer counter, wherein the output buffer counter is changed in a first manner when a unit of data is placed into an associated output buffer and wherein the output buffer counter is changed in a second manner when a unit of data is removed from the associated output buffer.

3. The apparatus of claim 2, further comprising

wherein the input buffer available indicator includes using an input buffer counter, wherein the input buffer counter is changed in a first manner when a unit of data is placed into an associated input buffer and wherein the input buffer counter is changed in a second manner when a unit of data is removed from the associated input buffer.

4. The apparatus of claim 3, wherein the first manner includes incrementing a counter and wherein the second manner includes decrementing the counter.

5. The apparatus of claim 4, wherein the status indicator indicates that a given task is ready to run when an output buffer associated with the given task has a predetermined negative output buffer counter value and when an input buffer associated with the given task has a predetermined positive input buffer counter.

6. The apparatus of claim 5, further comprising

an initialization value stored in a first counter prior to changing the first counter value.

7. The apparatus of claim 6, wherein the initialization value is a negative number that corresponds to a number of bytes of data to fulfill an output buffer, and wherein the initialization value is a positive number that corresponds to a number of bytes of data to fulfill an input buffer.

8. The apparatus of claim 7, further comprising

a port state indicator for indicating whether sufficient input and output buffers are available to a task.

9. The apparatus of claim 8, wherein the ports counter is decremented for 0-to-1 transitions and incremented for 1-to-0 transitions in an associated input buffer counter and wherein the ports counter is incremented for 0-to-1 transitions and is decremented for 1-to-0 transitions in an associated output buffer counter.

10. The apparatus of claim 9, wherein the status indicator is responsive to the high-order bit of the ports counter so that a transition of the high-order bit from 1 to 0 indicates that an associated task is ready to run.

11. A method for coordinating buffer use among tasks in a processing system, the method executing in the processing system, wherein the processing system includes a plurality of hardware nodes, wherein a task is executed on one or more of the hardware nodes, wherein a consuming task uses input buffers to obtain data and wherein a producing task uses output buffers to provide data, the method including the following

indicating the status of one or more buffers associated with a task;

maintaining an output buffer available indicator associated with an output buffer;

maintaining an input buffer available indicator associated with an input buffer; and

providing a status indicator for indicating that a task is ready to run based on a combination of the output buffer available indicator and the input buffer available indicator.

12. A computer-readable medium including instructions for coordinating buffer use among tasks in a processing system, wherein the processing system includes a plurality of hardware nodes, wherein a task is executed on one or more of the hardware nodes, wherein a consuming task uses input buffers to obtain data and wherein a producing task uses output buffers to provide data, the computer-readable medium including

one or more instructions for indicating the status of one or more buffers associated with a task;

one or more instructions for maintaining an output buffer available indicator associated with an output buffer;

one or more instructions for maintaining an input buffer available indicator associated with an input buffer; and

one or more instructions for providing a status indicator for indicating that a task is ready to run based on a combination of the output buffer available indicator and the input buffer available indicator.