Test structure for locating electromigration voids in dual damascene interconnects

• US 20040026693A1
• Filed: 08/07/2002
• Published: 02/12/2004
• Est. Priority Date: 08/07/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sullivan, Timothy D., Wang, Ping-Chuan, McLaughlin, Paul S.
• Granted Patent: US 6,995,392 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test structure is disclosed for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line. In an exemplary embodiment, the test structure includes a via portion the top of the interconnect via at the upper metallization line. In addition, a line portion extends from the via portion, wherein the line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.

Claims

1. A test structure for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line, the test structure comprising:

a via portion, said via portion overlying the top of the interconnect via, at the upper metallization line; and

a line portion extending from said via portion;

wherein said line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.

2. The test structure of claim 1, wherein said via portion overlaps the interconnect via.

3. The test structure of claim 1, wherein said via portion is centered over a top corner of the interconnect via.

4. The test structure of claim 1, wherein said line portion lies within the same metallization level as the upper metallization line.

5. The test structure of claim 1, wherein the semiconductor interconnect structure is a dual damascene structure.

6. A semiconductor interconnect structure, comprising:

a pair of lower metallization lines, connected by an upper metallization line through a pair of interconnect vias; and

a first test structure for locating electromigration voids in said upper metallization line and a first of said pair of interconnect vias, said first test structure further comprising;

a first via portion, said first via portion overlying the top of said first interconnect via, at said upper metallization line; and

a first line portion extending from said first via portion;

wherein first said line portion connects to a first external probing surface, in addition to a probing surface on a first of said pair of lower metallization lines, thereby allowing the identification of any electromigration voids present in said first interconnect via.

7. The interconnect structure of claim 6, wherein said first via portion overlaps said first interconnect via.

8. The interconnect structure of claim 6, wherein said first via portion is centered over a top corner of said first interconnect via.

9. The interconnect structure of claim 6, wherein said first line portion lies within the same metallization level as said upper metallization line.

10. The interconnect structure of claim 6, further comprising:

a second test structure for locating electromigration voids in said upper metallization line and a second of said pair of interconnect vias, said second test structure further comprising;

a second via portion, said second via portion overlying the top of said second interconnect via, at said upper metallization line; and

a second line portion extending from said second via portion;

wherein second said line portion connects to a second external probing surface, in addition to a probing surface on a second of said pair of lower metallization lines, thereby allowing the identification of any electromigration voids present in said second interconnect via.