Insulated gate field effect transistor having passivated schottky barriers to the channel
First Claim
1. A transistor, comprising a semiconductor channel disposed (i) nearby a gate configured to control conductance within the channel and (ii) in an electrical path between a source and a drain, at least one of which is made of a metal, wherein the channel and whichever of the source and/or the drain is/are made of the metal is/are separated by an interface layer so as to form a channel—
- interface layer—
source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω
-μ
m2.
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Accused Products
Abstract
A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel—interface layer—source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.
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Citations
45 Claims
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1. A transistor, comprising a semiconductor channel disposed (i) nearby a gate configured to control conductance within the channel and (ii) in an electrical path between a source and a drain, at least one of which is made of a metal, wherein the channel and whichever of the source and/or the drain is/are made of the metal is/are separated by an interface layer so as to form a channel—
- interface layer—
source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω
-μ
m2. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
- interface layer—
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17. A method, comprising:
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forming, on one or more surfaces of a semiconductor channel of a transistor, an interface layer; and
forming, on one or more surfaces of the interface layer opposite the semiconductor channel, a source or drain terminal for the transistor so as to create a channel—
interface layer—
source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω
-μ
m2. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. An electrical system comprising a circuit coupled to a transistor having a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, at least one of which is made of a metal, wherein the channel and whichever of the source and/or the drain is/are made of the metal is/are separated by an interface layer so as to form a channel—
- interface layer—
source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω
-μ
m2. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
- interface layer—
Specification