Insulated gate field effect transistor having passivated schottky barriers to the channel

• US 20040026736A1
• Filed: 01/14/2003
• Published: 02/12/2004
• Est. Priority Date: 08/12/2002
• Status: Active Grant

• Current Assignee: Acorn Semi, LLC (Acorn Technologies, Inc.)
• Original Assignee: Acorn Technologies, Inc.
• Inventors: Grupp, Daniel E., Connelly, Daniel J.
• Granted Patent: US 6,833,556 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28537 Deposition of Schottky electrodes
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 29/8126 : Thin film MESFET's
• CPC Class Codes: Y10S 438/958 : Passivation layer

Abstract

A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel—interface layer—source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm². The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

Claims

1. A transistor, comprising a semiconductor channel disposed (i) nearby a gate configured to control conductance within the channel and (ii) in an electrical path between a source and a drain, at least one of which is made of a metal, wherein the channel and whichever of the source and/or the drain is/are made of the metal is/are separated by an interface layer so as to form a channel—

interface layer—

source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω

-μ

m².

2. The transistor of claim 1 wherein the semiconductor channel is made of one of Si, Ge, SiGe, SiGeC, or siC.

3. The transistor of claim 1 wherein the metal comprises one of a pure metal, an alloy, or a refractory metal.

4. The transistor of claim 1 wherein the metal comprises aluminum.

5. The transistor of claim 1 wherein the specific contact resistance is less than or equal to approximately 100 Ω

-μ

m².

6. The transistor of claim 1 wherein the specific contact resistance is less than or equal to approximately 50 Ω

-μ

m².

7. The transistor of claim 1 wherein the specific contact resistance is less than or equal to approximately 10 Ω

-μ

m².

8. The transistor of claim 1 wherein the specific contact resistance is less than or equal to approximately 1 Ω

-μ

m².

9. The transistor of claim 1 wherein the interface layer includes a passivating material.

10. The transistor of claim 9 wherein the passivating material comprises one or more of a nitride of the semiconductor of the channel, a fluoride of the semiconductor of the channel, an oxide of the semiconductor of the channel, an oxynitride of the semiconductor of the channel, a hydride of the semiconductor of the channel and/or an arsenide of the semiconductor of the channel.

11. The transistor of claim 10 wherein the interface layer consists essentially of an amount of passivating material sufficient to terminate enough dangling bonds of a surface of the semiconductor channel so as to achieve chemical stability of the surface.

12. The transistor of claim 10 wherein the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel.

13. The transistor of claim 12 wherein the interface layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

14. The transistor of claim 9 wherein the interface layer further includes a separation layer.

15. The transistor of claim 14 wherein the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

16. The transistor of claim 1 wherein the semiconductor channel is separated from the gate by a dielectric.

17. A method, comprising:

forming, on one or more surfaces of a semiconductor channel of a transistor, an interface layer; and

forming, on one or more surfaces of the interface layer opposite the semiconductor channel, a source or drain terminal for the transistor so as to create a channel—

interface layer—

source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω

-μ

m².

18. The method of claim 17 wherein the semiconductor channel is formed by removing a portion of a semiconductor substrate that is not protected by a mask created at least in part by a gate structure formed above the semiconductor channel.

19. The method of claim 17 wherein the specific contact resistance is less than or equal to approximately 100 Ω

-μ

m².

20. The method of claim 17 wherein the specific contact resistance is less than or equal to approximately 50 Ω

-μ

m².

21. The method of claim 17 wherein the specific contact resistance is less than or equal to approximately 10 Ω

-μ

m².

22. The method of claim 17 wherein the specific contact resistance is less than or equal to approximately 1 Ω

-μ

m².

23. The method of claim 17 wherein the semiconductor channel is made of one of Si, Ge, SiGe, SiGeC, or sic.

24. The method of claim 23 wherein the gate is formed on a oxide layer disposed over the semiconductor channel.

25. The method of claim 24 wherein the oxide layer comprises a dielectric layer sufficiently thick enough to provide only capacitive coupling between the gate and the semiconductor channel.

26. The method of claim 24 wherein the oxide layer is formed over the semiconductor substrate by oxidizing the substrate.

27. The method of claim 26 wherein the gate is formed on the oxide layer by depositing a layer of metal on the oxide layer and removing a portion of the deposited layer of metal based on a lithographic exposure.

28. The method of claim 25 wherein the source or drain terminal is formed from a seed layer created by anisotropically depositing seed layer material on the semiconductor substrate.

29. The method of claim 27 wherein the interface layer is formed by covalently bonding at least a monolayer of a passivation material to the semiconductor channel.

30. The method of claim 29 wherein the passivation material comprises one or more of a nitride of the semiconductor channel, a fluoride of the semiconductor channel, an oxide of the semiconductor channel, an oxynitride of the semiconductor channel, a hydride of the semiconductor channel and/or an arsenide of the semiconductor channel.

31. The method of claim 29 wherein the interface layer includes a separation layer comprising a material different than the passivation material.

32. The method of claim 31 wherein the material that makes up the separation layer comprises an oxide of the semiconductor channel.

33. The method of claim 17 wherein the interface layer comprises an amount of a passivation material sufficient to terminate all or a sufficient number of dangling bonds of the one or more surfaces of the semiconductor channel to achieve chemical stability of the one or more surfaces.

34. An electrical system comprising a circuit coupled to a transistor having a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, at least one of which is made of a metal, wherein the channel and whichever of the source and/or the drain is/are made of the metal is/are separated by an interface layer so as to form a channel—

interface layer—

source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω

-μ

m².

35. The electrical system of claim 34 wherein the semiconductor channel is separated from the gate by a dielectric.

36. The electrical system of claim 35 wherein the specific contact resistance is less than or equal to approximately 100 Ω

-μ

m².

37. The electrical system of claim 35 wherein the specific contact resistance is less than or equal to approximately 50 Ω

-μ

m².

38. The electrical system of claim 35 wherein the specific contact resistance is less than or equal to approximately 10 Ω

-μ

m².

39. The electrical system of claim 35 wherein the specific contact resistance is less than or equal to approximately 1 Ω

-μ

m².

40. The electrical system of claim 35 wherein the semiconductor channel is made of one of Si, Ge, SiGe, SiGeC, or SiC.

41. The electrical system of claim 35 wherein the interface layer includes a passivating material.

42. The electrical system of claim 41 wherein the interface layer includes a separation layer comprising a material different than the passivation material.

43. The electrical system of claim 41 wherein the interface layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

44. The electrical system of claim 41 wherein the interface layer comprises an amount of passivating material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of a surface of the semiconductor channel in the region near the junction.

45. The electrical system of claim 44 wherein amount of passivating material comprises a monolayer.