MOS transistor device

• US 20040026737A1
• Filed: 05/28/2003
• Published: 02/12/2004
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Zundel, Markus
• Granted Patent: US 6,911,693 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In order to form a MOS transistor device with a particularly low on resistance with a good avalanche strength at the same time, it is proposed to define the position and/or the configuration of avalanche breakdown regions by a variation and/or a course of the width and/or of the depth of the respective trench structure and/or of the respective mesa regions.

Claims

1. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a first direction being a vertical direction, said trench structure having a lower region; and

an avalanche breakdown region disposed in said lower region of said trench structure, at least one of a position and a configuration of said avalanche breakdown region being determined and set in at least one lateral second direction, being substantially perpendicular to the first direction, by one at least one of a course of the trench structure and a variation of at least one of a width and a depth of the trench structure, the width being measured in a third direction being substantially perpendicular to the first and second directions, and the depth being measured in the first direction, and as a result forming a low on resistance of the MOS transistor device.

2. The MOS transistor device according to claim 1, wherein said semiconductor region having a mesa region being one of a region to adjacent to said trench structure and an intermediate region of said trench structure, at least one of said position and said configuration of said avalanche breakdown region is determined and set in the lateral second direction by at least one of a course of said mesa region and a variation of a width of said mesa region, said width being measured in the third direction.

3. The MOS transistor device according to claim 1, wherein said trench structure has a bottom region and said avalanche breakdown region is disposed in said bottom region.

4. A MOS transistor device, comprising:

a semiconductor region having a trench structure formed therein extending substantially in a first direction being a vertical direction into said semiconductor region, said semiconductor region further having a mesa region disposed one of adjacent to said trench structure and being an intermediate region of said trench structure, said trench structure having a lower region; and

an avalanche breakdown region formed in said lower region of said trench structure, at least one of a position and a configuration of said avalanche breakdown region being determined and set in at least one lateral second direction, being substantially perpendicular to the first direction, by at least one of a course and a variation of a width of said mesa region, said width being measured in a third direction being substantially perpendicular to the first and second directions, and as a result forming a low on resistance of the MOS transistor device.

5. The MOS transistor device according to claim 4, wherein said position and said configuration of said avalanche breakdown region is further determined and set in the lateral second direction, by at least one of a course and a variation of at least one of a width and a depth of said trench structure, said width being measured in the third direction, and said depth being measured in the first direction.

6. The MOS transistor device according to claim 4, wherein said mesa region has at least one region with a reduced width, and at least one of said position and said configuration of said avalanche breakdown region is one of defined by and formed by said region with said reduced breadth.

7. The MOS transistor device according to claim 6, wherein said trench structure has a region of increased width, said region with said reduced width of said mesa region is formed complementary to said region of increased width of said trench structure.

8. The MOS transistor device according to claim 6, wherein said region with said reduced width of said mesa region is defined by a region of a variation of said course of said trench structure.

9. The MOS transistor device according to claim 6, further comprising a contact region for a body region disposed one of in said region with said reduced width of said mesa region and in a vicinity thereof in said semiconductor region, said contact region formed at least one of as a body contact strip and disposed substantially perpendicularly to a course direction of said trench structure.

10. The MOS transistor device according to claims 4, further comprising:

a source region of a first conductivity type formed in said semiconductor region;

a drain region of said first conductivity type formed in said semiconductor region;

an insulation region; and

a gate electrode device formed substantially in an interior of said trench structure in a manner insulated by said insulation region.

11. The MOS transistor device according to claim 10, wherein said avalanche breakdown region is one of formed by a region of maximum electric field strength and defined by said region of maximum electric field strength.

12. The MOS transistor device according to claim 11, wherein said region of maximum electric field strength is formed between said source region and said drain region in direct proximity to said insulation region and to said lower region of said trench structure in a manner remote from said gate electrode device.

13. The MOS transistor device according to claim 11, wherein said region of maximum electric field strength is formed between said source region and said drain region in direct proximity to said lower region of said trench structure and in a manner remote from said gate electrode device.

14. The MOS transistor device according to claim 5, wherein said mesa region as said intermediate region, in a direction running substantially perpendicular to the first direction, has a width D_mesa which is less than said width D_trench of said trench structure in the first direction, such that D_mesa<

D_trench.

15. The MOS transistor device according to claim 4, wherein said mesa region as said intermediate region, in a direction running substantially perpendicular to the first direction and has a width D_mesa which is less than 2.5 times a maximum thickness D_GOX of said insulation region, such that:

D_mesa<

2.5·

D_GOX.

16. The MOS transistor device according to claim 10, further comprising a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device.

17. The MOS transistor device according to claim 16, wherein said body region is formed in a manner reinforced toward said drain region with a body reinforcement region of said second conductivity type.

18. The MOS transistor device according to claim 4, wherein said semiconductor region has a first lower region and a second lower region, and said trench structure reaching into said first lower region of said semiconductor region.

19. The MOS transistor device according to claim 4, further comprising a plurality of electrode devices disposed in said the trench structure.

20. The MOS transistor device according to claim 18,

further comprising a source terminal region connected to said source region;

further comprising a drain terminal region connected to said drain region, said drain region being formed, to avoid a rear-side contact connection of said semiconductor region to a greatest possible extent, on a same side of said semiconductor region as one of said source region and said source terminal region; and

wherein said first lower region being formed, as a terminal region and in a laterally offset manner extending to a surface region of said semiconductor region and to a surface of said second lower region.

21. The MOS transistor device according to claim 10, wherein the MOS transistor device is a field plate transistor device, and said insulation region has a field plate structure.

22. The MOS transistor device according to claim 21, further comprising a field oxide formed in said insulation region.

23. The MOS transistor device according to claim 22, wherein a thickness of said field oxide is greater than a thickness of said gate oxide in an upper region of said trench structure.

24. The MOS transistor device according to claim 4, wherein said trench structure has a bottom region and said avalanche breakdown region is disposed in said bottom region.

25. The MOS transistor device according to claim 8, wherein said region with said reduced width of said mesa region is defined by a region of said trench structure having a substantially constant width.

26. The MOS transistor device according to claim 13, further comprising:

a body region disposed in said semiconductor region; and

a region of a space charge zone formed in a presence of a breakdown voltage between said body region and said drain region, said region of maximum electric field strength disposed in said region of said space charge zone.

27. The MOS transistor device according to claim 10, further comprising a body region of a second conductivity type disposed substantially between said source region and said drain region in a manner insulated from said gate electrode device and in direct proximity to said source region.

28. The MOS transistor device according to claim 19, wherein said electrode devices include at least one of a plurality of gate regions and a plurality or source regions.

29. The MOS transistor device according to claim 20, wherein said first lower region is doped.

30. The MOS transistor device according to claim 22, wherein said mesa region has at least one region with a reduced width and said field oxide is formed in said trench structure adjacent to said region with said reduced width.

31. The MOS transistor device according to claim 19, wherein said contact region is disposed in said mesa region.