Semiconductor devices having strained dual channel layers

• US 20040026765A1
• Filed: 06/06/2003
• Published: 02/12/2004
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Fitzgerald, Eugene A., Lochtefeld, Anthony J., Currie, Matthew T., Leitz, Christopher W.
• Granted Patent: US 7,138,310 B2
• Time in Patent Office: Days
• US Class Current: 257/616
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

Claims

1. A semiconductor structure, comprising:

a strain-inducing substrate layer;

a compressively strained layer on the strain-inducing substrate layer, and comprising germanium having a concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, the compressively strained layer having a thickness less than its critical thickness; and

a tensilely strained layer comprising silicon on the compressively strained layer, the tensilely strained layer having a thickness less than its critical thickness.

2. The structure of claim 1, wherein the strain-inducing substrate layer comprises germanium having a concentration of at least 10 atomic %.

3. The structure of claim 1, wherein the strain-inducing substrate layer comprises an insulator.

4. The structure of claim 1, further comprising at least one p-channel component that primarily utilizes the compressively strained layer for a p-channel, and at least one n-channel component that primarily utilizes the tensilely strained layer for a n-channel.

5. The structure of claim 4, wherein the at least one p-channel component comprises a p-channel transistor, and the at the at least one n-channel component comprises an n-channel transistor.

6. The structure of claim 1, wherein the interfaces of the compressively strained layer and the tensilely strained layer are substantially free of misfit dislocations.

7. The structure of claim 1, wherein the concentration of the germanium of the strain-inducing strain-inducing substrate layer is less than approximately 30 atomic %.

8. The structure of claim 7, wherein the concentration of the germanium of the strain-inducing strain-inducing substrate layer is in a range of approximately 15 atomic % to approximately 20 atomic %.

9. The structure of claim 1, wherein the concentration of the germanium of the compressively strained layer is at most approximately 50 percentage points greater than the germanium concentration of the strain-inducing substrate layer.

10. The structure of claim 1, wherein a thickness of the compressively strained layer is in a range of approximately 3 nm to approximately 15 nm.

11. The structure of claim 10, wherein the thickness of the compressively strained layer is less than approximately 8 nm.

12. The structure of claim 1, wherein a thickness of the tensilely strained layer is in a range of approximately 5 nm to approximately 35 nm.

13. The structure of claim 12, wherein the thickness of the tensilely strained layer is in a range of approximately 12 nm to approximately 20 nm.

29. A semiconductor structure fabricated by the method of claim 12.

14. A semiconductor structure, comprising:

a substrate layer;

a compressively strained layer on the substrate layer, and having a strain of at least 1.2% and a thickness less than its critical thickness; and

a tensilely strained layer on the compressively strained layer, and having a strain of at least 0.4% and a thickness less than its critical thickness.

15. The structure of claim 14, wherein the tensilely strained layer has a strain of at most 1.2%.

16. The structure of claim 15, wherein the tensilely strained layer has a strain in a range of 0.6% to 0.8%.

17. The structure of claim 14, wherein the compressively strained layer has a strain of at most 2.0%.

18. A method for forming a semiconductor structure, the method comprising the steps of:

providing a substrate;

providing a compressively strained semiconductor on the substrate;

depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor;

forming on the first region a n-channel device that primarily utilizes the tensilely strained semiconductor for the n-channel; and

forming on the second region a p-channel device that primarily utilizes the compressively strained semiconductor for the p-channel.

19. The method of claim 18, wherein the thickness of the second region of the tensilely strained semiconductor is zero.

20. The method of claim 18, wherein depositing the tensilely strained semiconductor comprises forming at least a portion of the thickness of the first region of the tensilely strained semiconductor by depositing a first precursor and reacting a second precursor with the first precursor, whereby the first and second regions are provided with different thicknesses.

21. The method of claim 20, wherein depositing the tensilely strained semiconductor comprises repeating the steps of depositing the first precursor and reacting the second precursor with the first precursor to complete the thickness of the first region.

22. The method of claim 18, wherein the substrate comprises germanium, the compressively strained semiconductor comprises germanium having a greater concentration than a concentration of the germanium of the substrate, and the tensilely strained semiconductor comprises silicon.

23. The method of claim 18, wherein the thickness of the second region is at least great enough for growing a silicon dioxide layer having satisfactory integrity.

24. The method of claim 23, wherein the thickness of the second region is approximately 1 nm to 2 nm.

25. The method of claim 18, wherein the thickness of the second region is sufficiently small such that most of a charge carrier movement in a channel of the p-channel device moves in the compressively strained semiconductor.

26. The method of claim 18, wherein depositing the tensilely strained semiconductor comprises simultaneously depositing the second region of the tensilely strained semiconductor and a portion of the thickness of the first region of the tensilely strained semiconductor, and subsequently depositing a remaining portion of the thickness of the first region of the tensilely strained semiconductor.

27. The method of claim 18, wherein the substrate comprises a relaxed layer.

28. The method of claim 27, wherein the relaxed layer comprises germanium.

30. A method for fabricating a semiconductor structure, the method comprising:

providing a substrate comprising a strain-inducing Layer;

forming a dummy gate structure on the strain-inducing layer, the dummy gate structure comprising a dummy gate surrounded at least in part by a gate-defining material;

removing the dummy gate to expose a portion of the strain-inducing layer; and

depositing a strained semiconductor adjacent the strain-inducing layer, whereby the strained semiconductor can support at least a portion of a channel.

31. The method of claim 30, wherein the strained semiconductor comprises a compressively strained semiconductor.

32. The method of claim 30, wherein the strained semiconductor comprises a tensilely strained semiconductor.

33. The method of claim 32, further comprising depositing a compressively strained semiconductor on the exposed portion of the strain-inducing layer before depositing the tensilely strained semiconductor, whereby the compressively strained semiconductor and the tensilely strained semiconductor provide a dual channel layer.

34. The method of claim 33, further comprising forming at least one of a source and a drain in the substrate for a device associated with the dummy gate prior to depositing the compressively strained semiconductor, whereby a concentration profile of the compressively strained semiconductor is effectively preserved.

35. The method of claim 34, wherein the effectively preserved concentration profile is associated with an atomic concentration gradient of at least one decade per nanometer.

36. The method of claim 35, wherein the atomic concentration gradient is at least two decades per nanometer.

37. The method of claim 33, further comprising forming a contact on the substrate for a device associated with the dummy gate prior to depositing the compressively strained semiconductor, whereby a concentration profile of the compressively strained semiconductor is effectively preserved.

38. The method of claim 37, wherein the effectively preserved concentration profile is associated with an atomic concentration gradient of at least one decade per nanometer.

39. The method of claim 38, wherein the atomic concentration gradient is at least two decades per nanometer.

40. The method of claim 33, further comprising performing a plurality of process steps after depositing the tensilely strained semiconductor, the plurality of process steps occurring at temperatures no greater than approximately 600°

C.

41. The method of claim 40, wherein a concentration profile of the compressively strained semiconductor is associated with an atomic concentration gradient of at least one decade per nanometer after completion of the semiconductor structure.

42. The method of claim 41, wherein the atomic concentration gradient is at least two decades per nanometer.

43. The method of claim 33, further comprising forming a gate dielectric on the compressively strained semiconductor.

44. The method of claim 33, wherein the strain-inducing layer comprises SiGe.

45. The method of claim 44, wherein the compressively strained semiconductor comprises SiGe having a germanium concentration greater than a germanium concentration of the strain-inducing layer.

46. The method of claim 30, wherein the tensilely strained semiconductor consists essentially of silicon.

47. The method of claim 46, further comprising forming a gate dielectric by oxidizing a portion of the tensilely strained semiconductor.

48. A semiconductor structure fabricated by the method of claim 30.