High-density inter-die interconnect structure

• US 20040026771A1
• Filed: 08/08/2003
• Published: 02/12/2004
• Est. Priority Date: 09/10/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: John Russell Mcmacken, Paul Arthur Layman
• Inventors: McMacken, John Russell, Layman, Paul Arthur
• Granted Patent: US 7,045,835 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01058 Cerium [Ce]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

Claims

14. An integrated circuit device comprising:

a first integrated circuit including a plurality of discretely operable photo sensors, wherein an operational parameter of each of the plurality of photo sensors is related to the light incident on said first integrated circuit, and wherein said first integrated circuit further comprises a plurality of conductive interconnect elements each one in electrical communication with one or more of said plurality of photo sensors; and

a second integrated circuit having a plurality of connection pads formed on a surface thereof and in electrical communication with said plurality of conductive interconnect elements.

1. An integrated circuit device comprising:

a first integrated circuit comprising a plurality of discretely operable electrical elements and a plurality of conductive interconnect elements in electrical communication with one or more of said plurality of discretely operable-electrical elements; and

a second integrated circuit comprising operative circuitry and a plurality of connection pads formed on a surface thereof and in electrical communication with said plurality of conductive interconnect elements.

2. The integrated circuit device of claim 1 wherein the number of discretely operable electrical elements is equal to the number of interconnect elements.

3. The integrated circuit device of claim 1 wherein the pitch of the plurality of interconnect elements is equal to the pitch of the plurality of connection pads.

4. The integrated circuit device of claim 1 wherein the operative circuitry of the second integrated circuit operates in conjunction with the plurality of electrical elements of the first integrated circuit.

5. The integrated circuit device of claim 1 wherein the plurality of interconnect elements is equal to the plurality of discretely operable electrical elements.

6. The integrated circuit device of claim 1 wherein the plurality of interconnect elements comprise a plurality of conductive bumps.

7. The integrated circuit device of claim 6 wherein the plurality of conductive bumps are formed by forming a conductive layer over the plurality of electrical elements and selectively removing regions of the conductive layer such that the remaining regions form the conductive bumps.

8. The integrated circuit of claim 7 wherein the selective removal of regions of the conductive layer is controlled by a lithographic process using a mask to identify the regions to be removed.

9. The integrated circuit of claim 1 wherein each one of the plurality of discretely operable electrical elements comprises operative circuitry and a conductive pad in electrical communication with said operative circuitry, and wherein each one of said plurality of conductive pads is further in electrical communication with one of the plurality of interconnect elements, and wherein each one of said plurality of conductive pads is exposed through a lithographic process operative on the surface of the first integrated circuit to provide for the formation of the plurality of interconnect elements in electrical communication therewith.

10. The integrated circuit of claim 1 wherein each one of the plurality of conductive interconnect elements is affixed to one of the plurality of connection pads by the use of a conductive adhesive.

11. The integrated circuit device of claim 1 wherein the plurality of electrical elements are arranged in an array.

12. The integrated circuit device of claim 1 wherein the plurality of electrical elements are arranged in a linear pattern.

13. The integrated circuit device of claim 1 wherein the area devoted to the plurality of electrical elements on the first integrated circuit is maximized.

15. The integrated circuit device of claim 14 wherein the second integrated circuit comprises operative circuitry for determining the operational parameter of a photo sensor related to the incident light.

16. The integrated circuit device of claim 14 wherein the surface of the first integrated circuit exposed to the incident light is processed so as to maximize the light received by the plurality of photo sensors.

17. The integrated circuit device of claim 14 wherein the first integrated circuit comprises a semiconductor substrate of a first conductivity type and a plurality of spaced apart doped semiconductor regions of a second conductivity type formed in a surface of the semiconductor substrate, and wherein a reverse bias potential is applied to the semiconductor substrate and the doped regions so as to create a depletion region therebetween.

18. The integrated circuit device of claim 14 wherein the first integrated circuit comprises an image sensor array, and wherein the fill factor of the image sensor array is maximized.

19. The integrated circuit device of claim 18 wherein the conducting surface extending above the surface of the first integrated circuit comprises a conductive bump.

20. The integrated circuit of claim 19 wherein the conductive bumps are formed by forming a conductive layer over the plurality of electrical elements and selectively removing regions of the conductive layer such that the remaining regions form the conductive bumps.

21. The integrated circuit of claim 20 wherein the selective removal of regions of the conductive layer is controlled by a lithographic process using a mask to identify the regions to be removed.

22. The integrated circuit of claim 14 wherein each one of the plurality of discretely operable photo sensors comprises operative circuitry and a conductive pad in electrical communication with said operative circuitry, and wherein each one of said plurality of conductive pads is further in electrical communication with one of the plurality of interconnect elements, and wherein each one of said plurality of conductive pads is exposed through a lithographic process operative on the surface of the first integrated circuit to provide for the formation of the plurality of interconnect elements in electrical communication therewith.

23. The integrated circuit of claim 14 wherein each one of the plurality of conductive interconnect elements is affixed to one of the plurality of connection pads using a conductive adhesive.

24. The integrated circuit device of claim 14 wherein the plurality of photo sensors are arranged in an array.

25. The integrated circuit device of claim 14 wherein the plurality of photo sensors are arranged in a linear pattern.

17-1. The integrated circuit device of claim 14 wherein the plurality of conductive interconnect elements is equal in number to the plurality of photo sensors.

18-2. The integrated circuit device of claim 14 wherein each one of the plurality of conductive interconnect elements comprises a conductive surface extending above a surface of the first integrated circuit.

26. A method for fabricating an integrated circuit device comprising:

fabricating a first integrated circuit including a plurality of discretely operable electrical elements;

fabricating a plurality of conductive interconnect elements in electrical communication with one or more of said plurality of discretely operable electrical elements;

fabricating a second integrated circuit having a plurality of connection pads formed on a surface thereof; and

positioning each one of the plurality of conductive interconnect elements in electrical communication with one of the plurality of connection pads.

27. The method of claim 26 wherein the step of fabricating the plurality of conductive interconnect elements comprises forming a conductive layer over the plurality of electrical elements and selectively removing regions of the conductive layer such that the remaining regions form the conductive interconnect elements.

28. The method of claim 27 wherein the step of selectively removing further comprises applying a lithographic mask to the surface of the conductive layer and removing regions of the conductive layer as controlled by the lithographic mask.

29. The method of claim 26 wherein each one of the plurality of electrical elements comprises operative circuitry and a conductive pad in electrical communication with said operative circuitry, and wherein each one of said plurality of conductive pads is further in electrical communication with one of the plurality of interconnect elements, and wherein the method further comprises exposing each one of said plurality of conductive pads using a lithographic mask applied to the operative surface of the first integrated circuit and forming the plurality of interconnect elements in electrical communication therewith through the mask.

30. The method of claim 26 wherein the step of positioning further comprises affixing each one of the plurality of conductive interconnect elements to one of the plurality of connection pads using a conductive adhesive.

31. The method of claim 26 wherein one of each of the plurality of discretely operable electrical elements comprises a photo sensor.

32. The method of claim 26 wherein the plurality of photo sensors are fabricated by the step of doping a substrate of a first conductivity type with a dopant of a second conductivity type.