Motor control device

• US 20040027083A1
• Filed: 04/25/2003
• Published: 02/12/2004
• Est. Priority Date: 04/26/2002
• Status: Active Grant

• Current Assignee: Toyoda Koki Kabushiki Kaisha
• Original Assignee: Toyoda Koki Kabushiki Kaisha
• Inventors: Suzuki, Hiroshi
• Granted Patent: US 6,798,161 B2
• Time in Patent Office: Days
• US Class Current: 318/434
• CPC Class Codes: B62D 5/0487 detecting motor faults B62D5/0496 takes precedence
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02P 6/15 Controlling commutation time
• CPC Class Codes: H02P 6/28 Arrangements for controlling current H02P6/10 takes precedence

Abstract

The object of the present invention is to provide a motor control device capable of optimizing by actively controlling dead time even if FET characteristics change due to changes over time or the like.

In a motor control device 20, a motor drive device 24 is disposed for U-, V-, and W-phases. High-stage FETs 81U, 81V, 81W and low-stage FETs 82U, 82V, 82W are disposed in series and are turned on in an exclusive manner. Connection points 83U, 83V, 83W are disposed therebetween and send drive currents to the phases of a brushless DC motor 6. Shunt resistors RU, RV, RW are inserted in the circuit to detect current for each of the phases. Through-current is monitored to optimize dead time and perform efficient and responsive motor control. The CPU 21 monitors current values detected during dead time. If an irregularity is detected, the dead time is increased to prevent through-current.

Claims

1. A motor control device comprising:

high-stage FETs disposed on a power-supply side and low-stage FETs disposed on a ground side, said FETs being switching means connected in series in circuits disposed between an application point of a power supply and a ground point and associated with U, V, and W phases of a brushless DC motor, said FETs being selected in an exclusive manner;

connection points disposed between said high-level FETs and said low-stage FETs supplying drive currents to U-, V-, and W-phase motor coils based on combinations of open/close states of said high-level FETs and said low-stage FETs for each phase;

a current detecting means detecting currents in said circuits; and

a switch controlling means controlling said switching means and driving said brushless DC motor;

means for detecting irregular current detecting current at a predetermined timing using said current detecting means; and

means for evaluating motor drive circuit irregularities evaluating motor drive circuit irregularities based on current values detected by said irregular current detecting means.

2. A motor control device as described in claim 1 further comprising correcting means correcting a dead time setting based on a current value detected by said irregular current detecting means.

3. A motor control device as described in claim 1 or claim 2 wherein said irregular current detecting means detects a trailing edge when a gate signal for said U-, V-, or W-phase goes from on to off or a leading edge going from off to on and detects through-current during a dead time for each phase with said current detecting means using said timing as a reference.

4. A motor control device as described in claim 1 wherein:

said current detecting means is disposed so that current flowing through said low-stage FETs is detected; and

said irregular current detecting means detects when said controlling means is sending “

on”

gate signals to U-, V-, and W-phase high-stage FETs while sending “

off”

gate signals to all low-stage FETs and detects through-current in said phases at said timing using said current detecting means.

5. A motor control device as described in claim 1 wherein:

said current detecting means is disposed so that current flowing through said low-stage FETs is detected; and

said irregular current detecting means detects when said controlling means is sending “

on”

gate signals to U-, V-, and W-phase low-stage FETs while sending “

off”

gate signals to all high-stage FETs and detects through-current in said phases at said timing using said current detecting means.

6. A motor control device as described in claim 2 or claim 3 wherein, said correcting means reduces by a predetermined amount a dead time setting set up based on a turn-off dead time and a turn-on dead time set up ahead of time if a predetermined through-current is not detected by said irregular current detecting means, and, if said predetermined through-current is detected, said correcting means increases said dead time by a predetermined amount.

7. A motor control device as described in claim 6 wherein, if said through current is detected at a predetermined dead time value, said correcting means does not reduce said dead time below said dead time value at which said through-current was detected.

8. A motor control device as described in claim 6 or claim 7 wherein said controlling means sets dead time values independently for each of said phases.

9. A motor control device as described in any one of claim 6 through claim 8 wherein said correcting means sets said dead time setting value independently for turn-off dead time and turn-on dead time.