METHODOLOGY AND APPARATUS USING REAL-TIME OPTICAL SIGNAL FOR WAFER-LEVEL DEVICE DIELECTRICAL RELIABILITY STUDIES

• US 20040027149A1
• Filed: 08/07/2002
• Published: 02/12/2004
• Est. Priority Date: 08/07/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Aitren, John M., Nuttall, Gregory E., Dionne, Mark F., Chen, Fen, Condon, Kevin L.
• Granted Patent: US 6,788,093 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/1263 of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A method and structure tests devices on a wafer by applying an electrical bias to the devices and simultaneously monitoring emitted light from all of the devices. The emitted light indicates locations of defective devices and records time-based images of the emitted light across the wafer.

Claims

1. A method of testing devices on a wafer, said method comprising:

applying an electrical bias to said devices;

simultaneously monitoring emitted light from all of said devices, wherein said emitted light indicates times and locations of defective devices on said wafer; and

recording time-based optical signals of said emitted light across said wafer.

2. The method in claim 1, further comprising:

terminating connections between said electrical bias and said defective devices; and

repeating said monitoring and said terminating during a duration of said testing.

3. The method in claim 1, further comprising displaying said time-based optical signals during said testing.

4. The method in claim 1, further comprising mapping said device defects across said wafer on a time-line basis.

5. The method in claim 1, further comprising connecting said devices in parallel on said wafer by using a single electrical power source.

6. The method in claim 2, wherein said terminating comprises opening fuses to electrically disconnect said defective devices from said electrical bias.

7. The method in claim 1, further comprising connecting said devices in parallel on said wafer.

8. A method of testing devices on a wafer, said method comprising:

applying an electrical bias to said devices;

monitoring emitted light from said devices, wherein said emitted light indicates times and locations of defective devices;

terminating connections between said electrical bias and said defective devices; and

repeating said monitoring and said terminating during a duration of said testing.

9. The method in claim 8, wherein said monitoring comprises simultaneously monitoring emitted light from all of said devices.

10. The method in claim 8, further comprising recording time-based optical signals of said emitted light across said wafer.

11. The method in claim 8, further comprising mapping said defective devices across said wafer on a time-line basis.

12. The method in claim 8, further comprising connecting said devices in parallel on said wafer.

13. The method in claim 8, wherein said terminating comprises opening fuses to electrically disconnect said defective devices from said electrical bias.

14. A system for testing devices on a wafer, said system comprising:

an optical microscope adapted to apply an electrical bias to said devices;

a photon camera adapted to detect emitted light from said devices;

an image processor adapted to convert said emitted light into emitted light signals;

a monitor adapted to simultaneously monitor all of said emitted light signals, wherein said emitted light signals indicate locations of defective devices; and

a controller adapted to record time-based images of said emitted light across said wafer.

15. The system in claim 14, wherein said controller is adapted to terminate connections between said electrical bias and said defective devices.

16. The system in claim 15, wherein, during a testing cycle:

said monitor continues to monitor said devices after said connections to said defective devices are terminated; and

said controller continues to record said time-based optical signals and continues to terminate additional defective devices after said connections to said defective devices are terminated.

17. The system in claim 14, wherein said controller makes said time-based light emission signals available while said devices are being tested.

18. The system in claim 14, wherein said controller is adapted to map said device defects across said wafer on a time-line basis.

19. The system in claim 14, wherein said devices are connected in parallel on said wafer.

20. The system in claim 15, wherein said controller is adapted to open fuses to electrically disconnect said defective devices from said electrical bias.