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Method and apparatus for synchronously transferring data across multiple clock domains

  • US 20040027166A1
  • Filed: 08/08/2002
  • Published: 02/12/2004
  • Est. Priority Date: 08/08/2002
  • Status: Active Grant
First Claim
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1. An apparatus for adjusting a degree of alignment of clock phases of a first clock driving logic of a first clock domain of an integrated circuit (IC) and a second clock driving logic of a second clock domain of the IC, the apparatus comprising:

  • phase-alignment logic, the phase-alignment logic being configured to receive input from a user interface, the input automatically configuring the phase-alignment logic to delay the phase of at least one of the first and second clocks to adjust the degree of alignment of the phases of the first and second clocks.

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