Method and apparatus for synchronously transferring data across multiple clock domains

• US 20040027166A1
• Filed: 08/08/2002
• Published: 02/12/2004
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Meier, Peter J., Miller, Brian C., Groth, Cory, Mangum, Wayne G.
• Granted Patent: US 6,744,285 B2
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0037 Delay of clock signal

Abstract

A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.

Claims

1. An apparatus for adjusting a degree of alignment of clock phases of a first clock driving logic of a first clock domain of an integrated circuit (IC) and a second clock driving logic of a second clock domain of the IC, the apparatus comprising:

phase-alignment logic, the phase-alignment logic being configured to receive input from a user interface, the input automatically configuring the phase-alignment logic to delay the phase of at least one of the first and second clocks to adjust the degree of alignment of the phases of the first and second clocks.

2. The apparatus of claim 1, wherein said input configures the phase-alignment logic to cause at least one of the first and second clocks to be delayed in time, thereby causing the degree of alignment of the phases of the first and second clocks to be adjusted.

3. The apparatus of claim 2, wherein said input configures the phase-alignment logic to cause at least one of the first and second clocks to be delayed in time by selectively coupling one or more delay elements into paths of at least one of the first and second clock, each of said one or more delay elements having a known time delay associated therewith.

4. The apparatus of claim 1, wherein the phase-alignment logic comprises:

a first phase-alignment circuit, the first phase-alignment circuit receiving the first clock and a reference clock, the reference clock having a phase, the first phase-alignment circuit comprising first controllable time delay logic for delaying at least one of the first clock and the reference clock by a known, selectable time delay; and

a second phase-alignment circuit, the second phase alignment circuit receiving the second clock and said reference clock, the second phase-alignment circuit comprising second controllable time delay logic for delaying at least one of the second clock and the reference clock by a known, selectable time delay, wherein the degree of alignment of the phases of the first and second clock is adjusted by varying the phase relationship between of one of the first and second clocks and the reference clock.

5. The apparatus of claim 4, further comprising:

a user interface coupled to the first and second phase-alignment circuits, the user interface having an input device that a user can manipulate to control the phase relationship between of one of the first and second clocks and the reference clock.

6. The apparatus of claim 5, wherein when the user manipulates the input device, electrical signals are generated by the user interface and output to the first and second phase-alignment circuits, the electrical signals being received by at least one of the first and second controllable time delay logic and causing at least one of the first and second controllable time delay logic to delay at least one of the first clock, the second clock and the reference clock by said known, selectable time delay, wherein the degree by which said alignment of the phases of the first and second clock is adjusted depends on the values of said electrical signals.

7. The apparatus of claim 6, wherein the first and second controllable time delay logic each comprise first and second sets, respectively, of time delay elements having a known delay time associated therewith, each set of time delay elements comprising N delay elements, the first set of time delay elements of said first controllable time delay logic being associated with a path of the first clock, the second set of time delay elements of said first controllable time delay logic being associated with a path of the reference clock of the first phase-alignment circuit, the first set of time delay elements of said second controllable time delay logic being associated with a path of the second clock, the second set of time delay elements of said second controllable time delay logic being associated with a path of the reference clock of the second phase-alignment circuit, and wherein each of said delay elements is separately selectable according to said electrical signals, wherein when one of said delay elements is selected, the selected delay element is coupled into the path of the clock with which the selected delay element is associated thereby delaying the associated clock by the delay time associated with the selected delay element.

8. The apparatus of claim 7, wherein one or more of the delay elements of any of the sets of delay elements can be simultaneously selected and thereby coupled into the path of the clock with which the selected delay elements are associated, and wherein a total time delay in the associated clock is at least substantially equal to a sum of the delay times of the delay elements coupled into the path.

9. The apparatus of claim 8, wherein the phases of the first and second clocks are aligned when the phase of the first clock is aligned with the phase of the reference clock and the phase of the second clock is aligned with the phase of the reference clock.

10. The apparatus of claim 9, wherein an amount of clock skew between the first clock and the second clock is adjustable by aligning the phases of the second clock and the reference clock and by offsetting the phase relationship between the first clock and the reference clock by coupling one or more delay elements of the set of delay elements associated with the reference clock into the path of the reference clock.

11. The apparatus of claim 9, wherein an amount of clock skew between the first clock and the second clock is adjustable by aligning the phases of the second clock and the reference clock and by offsetting the phase relationship between the first clock and the reference clock by coupling one or more delay elements of the set of delay elements associated with the first clock into the path of the first clock.

12. The apparatus of claim 9, wherein a maximum clock skew margin associated with the first and second clocks is calculated by aligning the first and second clocks with the reference clock and then by increasing the delay of the reference clock by selectively coupling delay elements associated with the reference clock into the path of the reference clock until errors begin being detected in data signals output from the IC, wherein the maximum clock skew margin is equal to a sum of the time delays of the delay elements that were coupled into the path of the reference clock just before the errors began being detected in the data output from the IC.

13. The apparatus of claim 9, wherein a maximum clock skew margin associated with the first and second clocks is calculated by aligning the first and second clocks with the reference clock and then by increasing the delay of the first clock by selectively coupling delay elements associated with the first clock into the path of the first clock until errors begin being detected in data signals output from the IC, wherein the maximum clock skew margin is equal to a sum of the time delays of the delay elements that were coupled into the path of the first clock just before the errors began being detected in the data output from the IC.

14. A method for adjusting a degree of alignment of clock phases of a first clock driving logic of a first clock domain of an integrated circuit (IC) and a second clock driving logic of a second clock domain of the IC, the method comprising:

receiving input from a user interface in phase-alignment logic of the IC;

automatically configuring the phase-alignment logic in accordance with said input to delay at least one of the first and second clocks in time thereby adjusting a degree of alignment of the phases of the first and second clocks.

15. The method of claim 14, wherein said input automatically configures the phase-alignment logic to delay at least one of the first and second clocks in time by selectively causing one or more delay elements of the phase alignment logic to be coupled into paths of at least one of the first and second clocks, each of said one or more delay elements having a known time delay associated therewith.

16. The method of claim 14, wherein the step of automatically configuring comprises the steps of:

receiving the first clock and a reference clock in a first phase-alignment circuit of the phase alignment logic, the reference clock having a phase, the first phase-alignment circuit comprising first controllable time delay logic for delaying at least one of the first clock and the reference clock by a known, selectable time delay; and

receiving the second clock and said reference clock in a second phase-alignment circuit of the phase alignment logic, the second phase-alignment circuit comprising second controllable time delay logic for delaying at least one of the second clock and the reference clock by a known, selectable time delay; and

adjusting the degree of alignment of the phases of the first and second clocks by varying the phase relationship between at least one of the first and second clocks and the reference clock.