Duty-cycle correction circuit

• US 20040027182A1
• Filed: 03/20/2003
• Published: 02/12/2004
• Est. Priority Date: 03/28/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Minzoni, Alessandro, Brox, Martin
• Granted Patent: US 6,765,421 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

Claims

1. An apparatus comprising:

a first delay device for delaying a clock signal in response to a first control signal, thereby producing a delayed clock signal;

a first control signal generator configured to generate the first control signal on the basis of the clock signal and the delayed clock signal;

a second delay device for delaying a complementary clock signal in response to a second control signal, thereby producing a delayed complementary clock signal; and

a second control signal generator for generating the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal, the second control signal generator being configured to cause the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

2. The apparatus of claim 1, wherein the second control signal generator is configured to cause the pre-determined spacing to be half of a period of the clock signal.

3. The apparatus of claim 1, further comprising:

a first signal generator in communication with the first delay device and the first control signal generator, the first signal generator being configured to generate the clock signal in response to an external clock signal generated external to the apparatus, and

a second signal generator in communication with the second delay device, the second signal generator being configured to generate the complementary clock signal in response to an external complementary clock signal generated external to the apparatus.

4. The apparatus of claim 1, wherein the first control signal generator comprises:

a phase detector configured to generate a phase signal indicative of a phase difference between the clock signal and the delayed clock signal; and

a charge pump for generating the first control signal in response to the phase signal.

5. The apparatus of claim 1, wherein the second control signal generator comprises a duty ratio detector disposed to receive the delayed clock signal and the delayed complementary clock signal.

6. The apparatus of claim 5, wherein the second control signal generator further comprises a charge pump configured to generate the second control signal on the basis of the output of the duty ratio detector.

7. The apparatus of claim 6, wherein the charge pump comprises first and second switches controlled by an output of the duty ratio detector.

8. The apparatus of claim 7, wherein the charge pump further comprises a capacitor configured to store a charge that depends on states of the first and second switches.

9. The apparatus of claim 6, wherein the charge pump comprises:

first and second switches controlled by an output of the duty ratio detector; and

a capacitor configured to store a charge that depends on states of the first and second switches.

10. The apparatus of claim 7, wherein the first switch comprises a p-channel field-effect transistor and the second switch comprises an n-channel field-effect transistor.

11. The apparatus of claim 7, wherein the first and second switches comprise n-channel field-effect transistors.

12. The apparatus of claim 7, wherein the first and second switches comprise p-channel field-effect transistors.

13. The apparatus of claim 11, wherein the output of the duty cycle detector is configured to connect only to control terminals of the n-channel field-effect transistors, and wherein the first and second switches are configured such that the first and second delay devices impose the same delay when an external clock signal provided to the apparatus has a duty cycle of 0.5.

14. A method comprising:

delaying a clock signal in response to a first control signal, thereby generating a delayed clock signal therefrom;

generating a first control signal on the basis of the clock signal and the delayed clock signal;

delaying a complementary clock signal in response to a second control signal, thereby generating a delayed complementary clock signal therefrom;

generating a second control signal on the basis of the delayed clock signal and the delayed complementary clock signal, the second control signal being selected to cause the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

15. The method of claim 14, further comprising selecting the pre-determined spacing pre-determined spacing to be half of a period of the clock signal.

16. The method of claim 14, wherein:

delaying a clock signal comprises delaying a clock signal derived from an externally generated clock signal, and

delaying a complementary clock signal comprises delaying a complementary clock signal from an externally generated complementary clock signal.

17. The method of claim 14, wherein generating a second control signal comprises determining a duty ratio of the delayed clock signal and the delayed complementary clock signal, and selecting the second control signal on the basis of the duty ratio.

18. The method of claim 17, wherein determining a duty ratio comprises providing an output signal that is at

a first level at intervals between a rising edge of the delayed clock signal and a rising edge of the delayed complementary clock signal, and that is at

a second level at intervals between a rising edge of the delayed complementary clock signal and a rising edge of the delayed clock signal.

19. The method of claim 14, further comprising providing an analog delay-locked loop.

20. The method of claim 14, further comprising providing a digital delay-locked loop.

21. An apparatus for generating a first signal and a second signal separated from the first signal by a selected interval, the apparatus comprising:

a first delay device for delaying a clock signal by an interval controlled by a first control signal, thereby producing a delayed clock signal;

a second delay device for delaying a complementary clock signal by an interval controlled by a second control signal, thereby producing a delayed complementary clock signal;

a first control signal generator disposed to receive the clock signal and the delayed clock signal, the first control signal generator being configured to generate the first control signal on the basis of a phase difference between the clock signal and the delayed clock signal;

a second control signal generator disposed to receive the delayed clock signal and the delayed complementary clock signal, the second control signal generator including means for generating the second control signal on the basis of a phase difference between the delayed clock signal and the delayed complementary clock signal.