Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
First Claim
1. A nonvolatile memory array, comprising a) Flash memory cells in combination with EEPROM memory cells to form a nonvolatile memory, b) said Flash memory cells organized in blocks, c) said EEPROM memory cells organized in bytes, d) said Flash and EEPROM memory cells controlled to provide a simultaneous read and write capability, wherein said write operation includes first an erase operation and then a program operation.
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Accused Products
Abstract
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
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Citations
52 Claims
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1. A nonvolatile memory array, comprising
a) Flash memory cells in combination with EEPROM memory cells to form a nonvolatile memory, b) said Flash memory cells organized in blocks, c) said EEPROM memory cells organized in bytes, d) said Flash and EEPROM memory cells controlled to provide a simultaneous read and write capability, wherein said write operation includes first an erase operation and then a program operation.
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16. A simultaneous read and write nonvolatile memory, comprising:
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a) a means for forming an EEPROM memory cell that is scaleable and is compatible with bit line pitch of a Flash memory made from Flash memory cells, b) a means for forming a byte addressable EEPROM memory array using said EEPROM cell, c) a means for forming a block addressable Flash memory array from said Flash memory cell d) a means for organizing said EEPROM and Flash memory arrays to allow simultaneous read and write operations, wherein said write operation includes an erase operation followed by a program operation. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A precharge method for non-selected EEPROM memory cells to prevent punch through during program operation, comprising:
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a) applying a first voltage approximately equal to a precharge voltage to a selected bit line connected to a plurality of EEPROM memory cells, b) applying a second voltage that is higher than said precharge voltage to gates of select transistors of non-selected EEPROM memory cells of said plurality of EEPROM memory cells, c) applying zero volts to said select gates after a short time delay which turns off select transistors and leaves said precharge voltage on a source diffusion of said select transistors of said non-selected EEPROM memory cells. - View Dependent Claims (25, 26)
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27. A method for erase of EEPROM memory cells, comprising:
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a) resetting byte flags and data buffers to a logical “
0”
,b) loading new data into a data buffer, c) determining a need for an erase verify, d) selecting a deep erase if said erase verify is not required, e) applying an iterative erase if erase verify is required. - View Dependent Claims (28, 29, 30, 31)
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32. A method for programming of EEPROM memory cells, comprising:
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a) selecting a first address, b) transferring data to a program buffer, c) determining a need for an program verify, d) selecting a deep program operation to program a selected cell if said program verify is not required, e) applying an iterative program operation to program said cell if said program verify is required, f) incrementing a program address and returning to step b) if a last cell has not been programmed. - View Dependent Claims (33, 34, 35)
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36. A memory array configured from two-transistor EEPROM memory cells, comprising:
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a) a two transistor memory cell containing a select transistor and a storage transistor, b) an EEPROM memory array formed with a plurality of said two transistor memory cells organized into a plurality of memory bytes within a plurality of memory pages, c) a select gate signal selecting a memory byte from said plurality of memory bytes, d) said select gate signal selecting a source line signal to be connected to said sourceline of said selected memory byte, e) source lines connected to unselected memory bytes electrically float. - View Dependent Claims (37, 38)
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39. A vertical oriented EEPROM memory array, comprising:
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a) a column of two-transistor memory cells arranged into a plurality of rows of byte-wide segments, wherein each byte-wide segment is separately addressable, b) a byte-word line decoder located at an end of said column connecting to a word line of said byte-wide segments, c) an array of said two-transistor memory cells arranged in a plurality of columns of byte wide segments, wherein each column contains said byte-word line decoder. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. An horizontal oriented EEPROM memory array, comprising:
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a) a row of two transistor EEPROM memory cells arranged into a plurality of byte-wide segments, wherein each byte-wide segment of said plurality of byte-wide segments is separately addressable, b) a byte-word line decoder located at an end of said row, there from said byte-word line decoder connects to a word line of each byte-wide segment in said row, c) an array of said byte-wide segments arranged into a plurality of rows, wherein each row contains a byte-word line decoder. - View Dependent Claims (47, 48, 49)
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50. A byte-word line decoder, comprising:
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a) a decoding means for selecting a byte-word of data stored in an EEPROM memory array, b) an interconnection means for connecting said decoding means to a plurality of byte-word lines in said memory array, c) a wiring means for placing said interconnection means onto a plurality of metalization layers above a bit line metalization layer. - View Dependent Claims (51, 52)
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Specification