Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

• US 20040027856A1
• Filed: 01/24/2003
• Published: 02/12/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Tsao, Hsing-Ya, Ma, Han-Rei, Lee, Peter W., Hsu, Fu-Chang
• Granted Patent: US 6,850,438 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

Claims

1. A nonvolatile memory array, comprising

a) Flash memory cells in combination with EEPROM memory cells to form a nonvolatile memory,

b) said Flash memory cells organized in blocks,

c) said EEPROM memory cells organized in bytes,

d) said Flash and EEPROM memory cells controlled to provide a simultaneous read and write capability, wherein said write operation includes first an erase operation and then a program operation.

2. The array of claim 1, wherein said flash memory cells are erased by block and read by a byte or word or page contained within said block.

3. The array of claim 1 wherein said EEPROM memory cells are a combination of a stacked gate transistor of said Flash memory cell and a select transistor which produces a footprint size that is compatible with bit line pitch of said Flash memory cells.

4. The array of claim 3, wherein said footprint size allows common or separate bit lines and a minimum combined Flash and EEPROM memory size.

5. The array of claim 1, wherein said EEPROM memory cells are erased in units of bytes using FN channel tunneling, programmed in units of bits using CHE and read by a byte contained within a page.

6. The array of claim 5, wherein said page of EEPROM memory cells is oriented horizontally, or oriented vertically, or in a page comprising bytes in random address whereby each page contains a plurality of bytes.

7. The array of claim 1, further comprising a byte-word line decoder that selects said EEPROM memory cells organized by byte in a random order using an X-decoder that selects the select transistors of said EEPROM memory cells.

8. The array of claim 1, wherein said Flash memory cells and said EEPROM memory cells are organized within a same column addressable space sharing same bit line.

9. The array of claim 1, wherein said Flash memory cells and said EEPROM memory cells are organized in separate addressable space but share a data bus.

10. The array of claim 1, wherein said EEPROM memory cells are organized in a first memory bank containing a plurality of EEPROM arrays, each EEPROM array of said plurality of EEPROM arrays containing a separate byte word line decoder and sharing a same column addressable space, and wherein said Flash memory cells are organized in a second memory bank with different column address space from EEPROM arrays.

11. The array of claim 10, wherein said plurality of EEPROM arrays and said Flash array perform a simultaneous read-while-read, read-while-write and write-while-write operations.

12. The array of claim 1, wherein said EEPROM memory cells are organized into a plurality of EEPROM arrays within a plurality of memory banks, and further within each memory bank of said plurality of memory banks each EEPROM array of said plurality of EEPROM arrays contains a separate byte word line decode and shares column addressable space with each EEPROM array and with said Flash memory cells organized in a block array in each memory bank of said plurality of memory banks.

13. The array of claim 12, wherein any memory bank of said plurality of memory banks is capable of simultaneous read and write operations.

14. The array of claim 1, wherein said EEPROM memory cells are organized within a plurality of EEPROM memory banks, wherein each EEPROM memory bank contains a plurality of EEPROM arrays, each EEPROM array of said plurality of EEPROM arrays contain a separate byte word line decode and share column address space with each EEPROM array contained within said EEPROM memory bank, and wherein said Flash memory cells are organized into a plurality of Flash memory banks, and wherein said plurality of Flash memory banks and said EEPROM memory banks share address and data connections through bank multiplexers.

15. The array of claim 14, wherein any two EEPROM arrays, or any one Flash and one EEPROM array are capable of providing simultaneous read and write operations.

16. A simultaneous read and write nonvolatile memory, comprising:

a) a means for forming an EEPROM memory cell that is scaleable and is compatible with bit line pitch of a Flash memory made from Flash memory cells,

b) a means for forming a byte addressable EEPROM memory array using said EEPROM cell,

c) a means for forming a block addressable Flash memory array from said Flash memory cell

d) a means for organizing said EEPROM and Flash memory arrays to allow simultaneous read and write operations, wherein said write operation includes an erase operation followed by a program operation.

17. The memory of claim 16, wherein said means for forming said EEPROM memory cell further comprises combining a stacked gate transistor from said Flash memory cells with a select transistor that is sufficiently small to allow connection of the EEPROM to a bit line pitch of said Flash memory cells.

18. The memory of claim 16, wherein the means for forming said byte addressable EEPROM memory contains addressable bytes within a page that is oriented vertically and having common bit lines between said bytes.

19. The memory of claim 16, wherein the means for forming said byte addressable EEPROM contains a plurality of addressable bytes within a page comprising bytes in a random address.

20. The memory of claim 16, wherein the means for forming said byte addressable EEPROM contains addressable bytes within a page that is oriented horizontally and containing a common word line between said bytes.

21. The memory of claim 16, wherein the means for organizing said EEPROM and Flash memory arrays are arranged into separate memory banks and provide simultaneous read-while-read, read-while-write and write-while-write operations.

22. The memory of claim 16, wherein the means for organizing said EEPROM and Flash memory arrays forms a plurality of byte addressable EEPROM arrays and a Flash memory array that share bit lines in a column addressable space that is capable of simultaneous read-while-read, read-while-erase and write-while-write operations.

23. The memory of claim 16, wherein the means for organizing said EEPROM and Flash memory arrays further comprising:

a) a first plurality of memory banks, each containing a plurality of said byte addressable EEPROM memory arrays, wherein each array contains a byte word line decoder,

b) a second plurality of memory banks, each containing said Flash memory array,

c) any two EEPROM memory arrays and any two Flash memory arrays capable of simultaneous read-while-read, read-while-write and write-while write operations.

24. A precharge method for non-selected EEPROM memory cells to prevent punch through during program operation, comprising:

a) applying a first voltage approximately equal to a precharge voltage to a selected bit line connected to a plurality of EEPROM memory cells,

b) applying a second voltage that is higher than said precharge voltage to gates of select transistors of non-selected EEPROM memory cells of said plurality of EEPROM memory cells,

c) applying zero volts to said select gates after a short time delay which turns off select transistors and leaves said precharge voltage on a source diffusion of said select transistors of said non-selected EEPROM memory cells.

25. The method of claim 24, wherein said precharge voltage reduces a drain to source voltage of said select transistors of said non-selected EEPROM cells to below device punch through which allows said select transistors of said plurality of EEPROM cells to have a short channel.

26. The method of claim 24, wherein said second voltage is of an amplitude such as to allow said precharge voltage to be passed through the source diffusion of said select transistors.

27. A method for erase of EEPROM memory cells, comprising:

a) resetting byte flags and data buffers to a logical “

0”

,

b) loading new data into a data buffer,

c) determining a need for an erase verify,

d) selecting a deep erase if said erase verify is not required,

e) applying an iterative erase if erase verify is required.

28. The method of claim 27, wherein said loading new data allows bits of byte flags to be set when a selected data need to be changed.

29. The method of claim 27, wherein said determining the need for erase verify is an option to be selected by a memory designer.

30. The method of claim 27, wherein said selecting deep erase has a further selection of said deep erase by a single byte, multiple bytes or a whole page.

31. The method of claim 27, wherein said applying of said iterative erase has a further selection of said iterative erase by a single byte, multiple bytes or a whole page.

32. A method for programming of EEPROM memory cells, comprising:

a) selecting a first address,

b) transferring data to a program buffer,

c) determining a need for an program verify,

d) selecting a deep program operation to program a selected cell if said program verify is not required,

e) applying an iterative program operation to program said cell if said program verify is required,

f) incrementing a program address and returning to step b) if a last cell has not been programmed.

33. The method of claim 32, wherein said determining the need for iterative programming is an option to be selected by a memory designer.

34. The method of claim 32, wherein said transferring data to a program buffer bit by bit is controlled by an address counter to enable said selected cell to be programmed.

35. The method of claim 34, wherein the transferring data controls a few bits for simultaneous programming.

36. A memory array configured from two-transistor EEPROM memory cells, comprising:

a) a two transistor memory cell containing a select transistor and a storage transistor,

b) an EEPROM memory array formed with a plurality of said two transistor memory cells organized into a plurality of memory bytes within a plurality of memory pages,

c) a select gate signal selecting a memory byte from said plurality of memory bytes,

d) said select gate signal selecting a source line signal to be connected to said sourceline of said selected memory byte,

e) source lines connected to unselected memory bytes electrically float.

37. The memory array of claim 36, wherein said source line is shared between two adjacent memory bytes within a page of said plurality of pages.

38. The memory array of claim 36, wherein all source lines within said page are connected together.

39. A vertical oriented EEPROM memory array, comprising:

a) a column of two-transistor memory cells arranged into a plurality of rows of byte-wide segments, wherein each byte-wide segment is separately addressable,

b) a byte-word line decoder located at an end of said column connecting to a word line of said byte-wide segments,

c) an array of said two-transistor memory cells arranged in a plurality of columns of byte wide segments, wherein each column contains said byte-word line decoder.

40. The memory array of claim 39, further comprising:

a) a first plurality of metal lines connecting bit lines and a source line to said memory cells in each said byte-wide segment contained within each column of said plurality of columns and an output of said byte-word line decoder to said word line of a first byte-wide segment,

b) a second plurality of metal lines connecting between said byte-word line decoder and said word line of each additional byte-wide segment beyond said first byte-wide segment that are contained within each column of said plurality of columns.

41. The memory array of claim 40, wherein said first plurality of metal lines are routed along a length and distributed across a width of each said column in a first layer of metal lines.

42. The memory array of claim 41, wherein said first plurality of metal lines connect to eight bit lines, one source line and one word line.

43. The memory array of claim 40, wherein said second plurality of metal lines are routed along a length and distributed across the width of each said column in a plurality of wiring layers of metal lines located above a first layer of metal lines.

44. The memory array of claim 43, wherein said second plurality of metal lines connect separately to byte segments in a column and are routed in groups of ten metal lines on each wiring layer above said first wiring layer.

45. The memory array of claim 43, wherein said second plurality of metal lines are clustered together with a plurality of global word lines at the side of said column of byte-wide segments when a number of wiring layers is limited.

46. An horizontal oriented EEPROM memory array, comprising:

a) a row of two transistor EEPROM memory cells arranged into a plurality of byte-wide segments, wherein each byte-wide segment of said plurality of byte-wide segments is separately addressable,

b) a byte-word line decoder located at an end of said row, there from said byte-word line decoder connects to a word line of each byte-wide segment in said row,

c) an array of said byte-wide segments arranged into a plurality of rows, wherein each row contains a byte-word line decoder.

47. The memory array of claim 46, further comprising:

a) a first plurality of metal lines connecting bit lines and a source line in columns to the memory cells in each byte-wide segment of said plurality of byte-wide segments,

b) a second plurality of metal lines connecting said byte-word line decoder to said each byte wide segment contained within each row of said plurality of rows.

48. The memory array of claim 47, wherein said first plurality of metal lines are routed in columns of byte-wide segments.

49. The memory array of claim 47, wherein said second plurality of metal lines are routed in rows between said byte-word line decoder and said byte-wide segments in said row.

50. A byte-word line decoder, comprising:

a) a decoding means for selecting a byte-word of data stored in an EEPROM memory array,

b) an interconnection means for connecting said decoding means to a plurality of byte-word lines in said memory array,

c) a wiring means for placing said interconnection means onto a plurality of metalization layers above a bit line metalization layer.

51. The decoder of claim 50, wherein said wiring means places byte-word lines within said plurality of metalization layers located above a column of byte-word bit lines on said bit line metalization layer and running in parallel with said byte-word bit lines.

52. The decoder means of claim 50, wherein said wiring means places byte-word lines within said plurality of metalization layers located above a plurality of columns of byte-word bit lines on said bit line metalization layer and running orthogonal to said byte-word bit lines.