Programming and erasing methods for a reference cell of an NROM array

• US 20040027871A1
• Filed: 11/21/2002
• Published: 02/12/2004
• Est. Priority Date: 05/04/2000
• Status: Abandoned Application

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo, Bloom, Ilan
• Application Number:
  US10/300,924
• Publication Number:
  US 20040027871A1
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Claims

1. A method for programming a reference cell of a memory array, the method using programming pulses, the method comprising the steps of:

if a threshold voltage of said reference cell is below an interim target level, raising a drain voltage for a next programming pulse, otherwise, setting said drain voltage for the next programming pulse at a fixed level not higher than a current level; and

providing programming pulses using said fixed drain voltage level until said threshold voltage level is at or above a final target level above said interim target level.

2. A method according to claim 1 wherein for said step of providing, said programming pulses have a different duration than said programming pulse for said step of raising.

3. A method according to claim 1 wherein said interim target level is in the range of 100-400 mV below said final target level.

4. A method according to claim 1 wherein said interim target level is below said final target level by an amount generally not smaller than an expected threshold voltage change due to said programming pulses of said raising step.

5. A method according to claim 1 and also comprising the step of measuring said programmed threshold voltage level after each programming pulse.

6. A method according to claim 1 and also comprising the step of determining after each programming pulse if the programmed threshold voltage is above or below the target level.

7. A method for programming a reference cell of a memory array, the method comprising:

fast programming of said reference cell until a threshold voltage level of said reference cell is above an interim target level; and

slow programming of said reference cell until said threshold voltage level is above a final target level which is above said interim target level.

8. A method according to claim 7 wherein said fast programming comprises providing programming pulses and changing a drain voltage level between programming pulses.

9. A method according to claim 7 wherein said slow programming comprises maintaining a generally constant drain voltage level between programming pulses.

10. A method according to claim 7 wherein said interim target level is below said final verify level by an amount generally not smaller than the expected threshold voltage change due to said programming pulses of said fast programming step.

11. A method according to claim 7 wherein said steps of programming include providing programming pulses and also comprising the step of measuring said threshold voltage level of said reference cell after each programming pulse.

12. A method for programming a reference cell of a memory array, the method comprising the steps of:

programming said reference cell with large programming steps until a threshold voltage level of said reference cell is above an interim target level; and

programming said reference cell with small programming steps until said threshold voltage level is above a final target level.

13. A method according to claim 12 wherein said programming with large programming steps comprises providing programming pulses and changing a drain voltage level between programming pulses.

14. A method according to claim 12 wherein said programming with small programming steps comprises maintaining a generally constant drain voltage level between programming pulses.

15. A method according to claim 12 wherein said interim target level is below said final verify level by an amount generally not smaller than an expected threshold voltage change due to said large programming steps.

16. A method according to claim 12 wherein said steps of programming include providing programming pulses and also comprising the step of measuring said threshold voltage level of said reference cell after each programming pulse.