Programmable integrated DiSEqC transceiver

• US 20040028149A1
• Filed: 04/11/2003
• Published: 02/12/2004
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Krafft, Stephen Edward, Pai, Patrick K. D., Cheng, Jasmine Sai Ying, Nguyen, Nicholas Huu
• Granted Patent: US 7,336,706 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H03K 5/1534 Transition or edge detectors
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

Programmable integrated Digital Satellite Equipment Control (DiSEqC) transceiver. The DiSEqC functionality is integrated onto a semiconductor device. Rather than perform the DiSEqC protocol in software, the DiSEqC protocol is implemented in hardware thereby providing more reliable demodulation and improved robustness. The device'"'"'s functionality may employ much more reliable communication schemes that are enabled by the hardware/integrated approach of implementing the DiSEqC protocol. The integrated approach allows extensive programmability of the various operational parameters thereby greatly improving the ease of future backward compatibility with legacy devices; devices employing this integrated DiSEqC functionality may be easily updated to conform to future enhancements of the DiSEqC protocol. Some of the now-improved features enabled by the integrated/monolithic approach of DiSEqC include programmable tone amplitude, programmable PWK duty cycle, programmable length of messages, programmable time between messages (before and after), programmable voltage thresholds, tone transmit amplitude detection, improved voltage regulator feedback.

Claims

1. An integrated circuit, comprising:

a master device functional block that includes a transmitter functional block that is operable to generate a PWK (Pulse Width Key) command signal comprising a plurality of messages;

a voltage regulator device functional block, communicatively coupled to the master device functional block, that is operable to regulate a voltage level of the PWK command signal; and

wherein the master device functional block is operable to program at least one of an amplitude of the PWK command signal, a frequency of the PWK command signal, a duty cycle of the PWK command signal, a message length of a message within the plurality of messages, a time between messages of the plurality of messages, and a DC (Direct Current) offset level of the PWK command signal.

2. The integrated circuit of claim 1, wherein:

the voltage regulator device functional block is operable to communicatively couple the PWK command signal via a bus to at least one additional integrated circuit that includes a slave device functional block; and

wherein the master device functional block is also operable to program a transmit enable feature to eliminate bus glitches on the bus.

3. The integrated circuit of claim 2, wherein:

the master device functional block also includes a receiver functional block that is operable to receive a signal from the at least one additional integrated circuit that includes the slave device functional block; and

the integrated circuit and the at least one additional integrated circuit perform two way communication.

4. The integrated circuit of claim 2, wherein the integrated circuit is a satellite communications receiver decoder integrated circuit.

5. The integrated circuit of claim 1, wherein voltage control feedback, representative of the PWK command signal, is provided back to the voltage regulator device functional block.

6. An integrated circuit, comprising:

a master device functional block that includes a transmitter functional block that is operable to generate a PWK (Pulse Width Key) command signal comprising a plurality of messages;

a voltage regulator device functional block, communicatively coupled to the master device functional block, that is operable to regulate a voltage level of the PWK command signal;

wherein the voltage regulator device functional block is operable to communicatively couple the PWK command signal via a bus to at least one additional integrated circuit that includes a slave device functional block;

wherein the master device functional block also includes a receiver functional block that is operable to receive a signal from the at least one additional integrated circuit that includes the slave device functional block; and

wherein the master device functional block is operable to program at least one of an amplitude of the PWK command signal, a frequency of the PWK command signal, a duty cycle of the PWK command signal, a message length of a message within the plurality of messages, a time between messages of the plurality of messages, a transmit enable feature to eliminate bus glitches on the bus, and a DC (Direct Current) offset level of the PWK command signal.

7. The integrated circuit of claim 6, wherein the integrated circuit is a satellite communications receiver decoder integrated circuit.

8. The integrated circuit of claim 6, wherein voltage control feedback, representative of the PWK command signal, is provided back to the voltage regulator device functional block.

9. The integrated circuit of claim 6, wherein:

the master device functional block is an integrated DiSEqC (Digital Satellite Equipment Control) master device functional block;

the transmitter functional block, within the integrated DiSEqC master device functional block, includes;

a DDFS (Direct Digital Frequency Synthesizer) that generates a digital voltage waveform for use in PWK (Pulse Width Key) signaling;

a DC (Direct Current) control functional block that is operable to add a DC voltage offset to the digital voltage waveform;

a DAC (Digital to Analog Converter) that is operable to convert the digital voltage waveform to an analog voltage signal; and

an on-chip amplifier that is operable to increase a magnitude of the analog voltage signal.

10. The integrated circuit of claim 6, wherein the integrated circuit is implemented within at least one of a satellite receiver, a HDTV (High Definition Television) set top box receiver, a receiver, a DiSEqC (Digital Satellite Equipment Control) transceiver, and an advanced modulation satellite receiver.

11. A satellite communications receiver decoder integrated circuit, the integrated circuit comprising:

an integrated DiSEqC (Digital Satellite Equipment Control) master device that is operable to generate a PWK (Pulse Width Key) command signal that includes a plurality of DiSEqC messages;

a DiSEqC voltage regulator device, communicatively coupled to the integrated DiSEqC master device, that is operable to regulate a voltage level of the PWK command signal;

wherein the DiSEqC voltage regulator device is operable to communicatively couple the PWK command signal to a DiSEqC slave device via a DiSEqC bus; and

wherein the integrated DiSEqC master device is operable to program at least one of an amplitude of the PWK command signal, a frequency of the PWK command signal, a duty cycle of the PWK command signal, a message length of a DiSEqC message within the plurality of DiSEqC messages, a time between DiSEqC messages of the plurality of DiSEqC messages, a transmit enable feature to eliminate bus glitches on the DiSEqC bus, and a DC (Direct Current) offset level of the PWK command signal.

12. The integrated circuit of claim 11, wherein the integrated DiSEqC master device includes a transmitter functional block, a receiver functional block, and a finite state machine controller;

and

wherein the transmitter functional block includes;

a DDFS (Direct Digital Frequency Synthesizer) that generates a digital voltage waveform for use in PWK (Pulse Width Key) signaling;

a DC (Direct Current) control functional block that is operable to add a DC voltage offset to the digital voltage waveform;

a DAC (Digital to Analog Converter) that is operable to convert the digital voltage waveform to an analog voltage signal;

an on-chip amplifier that is operable to increase a magnitude of the analog voltage signal;

wherein the receiver functional block is operable to program a detection range for use by the DiSEqC master device when performing envelope detection; and

wherein the finite state machine controller governs operation of the transmitter functional block using a predetermined number of operational states.

13. The integrated circuit of claim 12, wherein the DDFS receives a programmable FCW (Frequency Control Word) that is used to select a frequency of the PWK command signal.

14. The integrated circuit of claim 13, wherein the frequency of the PWK command signal is approximately 22 kHz.

15. The integrated circuit of claim 11, wherein the integrated DiSEqC master device includes a receiver functional block that is operable to receive a signal from the DiSEqC slave device.

16. The integrated circuit of claim 11, wherein voltage control feedback, representative of the PWK command signal, is provided back to the DiSEqC voltage regulator device.

17. The integrated circuit of claim 11, wherein voltage control feedback, representative of the PWK command signal, is provided back to the integrated DiSEqC master device.

18. The integrated circuit of claim 11, wherein the integrated DiSEqC master device includes a transmitter functional block;

and

the transmitter functional block performs tone saturation and tone clipping when generating one of the DiSEqC messages of the plurality of DiSEqC messages.

19. The integrated circuit of claim 11, wherein the DiSEqC slave device performs PWK demodulation of the PWK command signal received from the DiSEqC voltage regulator device via the DiSEqC bus and provides the demodulated PWK command signal to a microprocessor.

20. The integrated circuit of claim 11, wherein the integrated circuit is implemented within at least one of a satellite receiver, a HDTV (High Definition Television) set top box receiver, a receiver, a DiSEqC transceiver, and an advanced modulation satellite receiver.

21. A satellite communications receiver decoder integrated circuit, the integrated circuit comprising:

an integrated DiSEqC (Digital Satellite Equipment Control) master device that is operable to generate a PWK (Pulse Width Key) command signal that includes a plurality of DiSEqC messages, the integrated DiSEqC master device comprising;

a transmitter functional block, comprising;

a DDFS (Direct Digital Frequency Synthesizer) that generates a digital voltage waveform for use in PWK (Pulse Width Key) signaling;

a DC (Direct Current) control functional block that is operable to add a DC voltage offset to the digital voltage waveform;

a DAC (Digital to Analog Converter) that is operable to convert the digital voltage waveform to an analog voltage waveform;

an on-chip amplifier that is operable to increase a magnitude of the analog voltage waveform thereby generating the PWK command signal;

a receiver functional block that is operable to program a detection range for use by the DiSEqC master device when performing envelope detection;

a finite state machine controller that governs operation of the transmitter functional block using a predetermined number of operational states;

a DiSEqC voltage regulator device, communicatively coupled to the integrated DiSEqC master device, that is operable to regulate a voltage level of the PWK command signal;

wherein the DiSEqC voltage regulator device is operable to communicatively couple the PWK command signal to a DiSEqC slave device via a DiSEqC bus;

wherein voltage control feedback, representative of the PWK command signal, is provided back to at least one of the integrated DiSEqC master device and the DiSEqC voltage regulator device; and

wherein the integrated DiSEqC master device is operable to program at least one of an amplitude of the PWK command signal, a frequency of the PWK command signal, a duty cycle of the PWK command signal, a message length of a DiSEqC message within the plurality of DiSEqC messages, a time between DiSEqC messages of the plurality of DiSEqC messages, a transmit enable feature to eliminate bus glitches on the DiSEqC bus, and a DC offset level of the PWK command signal.

22. The integrated circuit of claim 21, wherein the DDFS receives a programmable FCW (Frequency Control Word) that is used to select a frequency of the PWK command signal.

23. The integrated circuit of claim 22, wherein the frequency of the PWK command signal is approximately 22 kHz.

24. The integrated circuit of claim 21, wherein the receiver functional block within the integrated DiSEqC master device receives a signal from the DiSEqC slave device.

25. The integrated circuit of claim 21, wherein the voltage level of the PWK command signal is a voltage between approximately 12 V and approximately 21 V.

26. The integrated circuit of claim 21, wherein the transmitter functional block performs tone saturation and tone clipping when generating one of the DiSEqC messages of the plurality of DiSEqC messages.

27. The integrated circuit of claim 21, wherein the DiSEqC slave device performs PWK demodulation of the PWK command signal received from the DiSEqC voltage regulator device via the DiSEqC bus and provides the demodulated PWK command signal to a microprocessor.

28. The integrated circuit of claim 21, wherein the integrated circuit is implemented within at least one of a satellite receiver, a HDTV (High Definition Television) set top box receiver, a receiver, a DiSEqC transceiver, and an advanced modulation satellite receiver.

29. An integrated DiSEqC (Digital Satellite Equipment Control) master device that is operable to generate a PWK (Pulse Width Key) command signal that includes a plurality of DiSEqC messages, the integrated DiSEqC master device comprising:

a transmitter functional block, comprising;

a DDFS (Direct Digital Frequency Synthesizer) that generates a digital voltage waveform for use in PWK signaling;

a DC (Direct Current) control functional block that is operable to add a DC voltage offset to the digital voltage waveform;

a DAC (Digital to Analog Converter) that is operable to convert the digital voltage waveform to an analog voltage waveform;

an on-chip amplifier that is operable to increase a magnitude of the analog voltage waveform thereby generating the PWK command signal;

a finite state machine controller that governs operation of the transmitter functional block using a predetermined number of operational states; and

wherein the integrated DiSEqC master device is implemented as a functional block within a satellite communications receiver decoder integrated circuit.

30. The integrated DiSEqC master device of claim 29, wherein the integrated DiSEqC master device also includes a receiver functional block that is operable to receive a signal from a DiSEqC slave device.

31. The integrated DiSEqC master device of claim 30, wherein the DDFS receives a programmable FCW (Frequency Control Word) that is used to select a frequency of the PWK command signal.

32. The integrated DiSEqC master device of claim 31, wherein the frequency of the PWK command signal is approximately 22 kHz.

33. The integrated DiSEqC master device of claim 29, wherein the integrated DiSEqC master device is communicatively coupled to a DiSEqC voltage regulator device that is operable to regulate a voltage level of the PWK command signal.

34. The integrated DiSEqC master device of claim 33, wherein the DiSEqC voltage regulator device is communicatively coupled to a DiSEqC slave device via a DiSEqC bus.

35. The integrated DiSEqC master device of claim 29, wherein the transmitter functional block performs tone saturation and tone clipping when generating one of the DiSEqC messages of the plurality of DiSEqC messages.

36. The integrated DiSEqC master device of claim 29, wherein the integrated DiSEqC master device is implemented within at least one of a satellite receiver, a HDTV (High Definition Television) set top box receiver, a receiver, a DiSEqC transceiver, and an advanced modulation satellite receiver.