Semiconductor device and method of fabricating the same

• US 20040029338A1
• Filed: 06/24/2003
• Published: 02/12/2004
• Est. Priority Date: 01/29/1999
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukunaga, Takeshi, Ikeda, Takayuki, Yamazaki, Shunpei
• Granted Patent: US 6,955,953 B2
• Time in Patent Office: Days
• US Class Current: 438/202
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

There is provided a semiconductor device including a storage capacitor having sufficient capacity and a minimum area. The storage capacitor of a pixel region has such a structure that a first storage capacitor and a second storage capacitor are stacked one on top of the other and are connected in parallel with each other. At that time, the first storage capacitor comprises a first capacitance electrode formed in the same layer as a drain region, a first dielectric, and a second capacitance electrode formed in the same layer as a gate wiring. The second storage capacitor comprises the second capacitance electrode, a second dielectric, and a third capacitance electrode formed in the same layer as a light-shielding film.

Claims

1. A method of fabricating a semiconductor device comprises steps of:

forming an active layer over a substrate;

forming an insulating film containing silicon on said active layer;

exposing a portion of said active layer by removing a part of said insulating film containing silicon;

forming a first insulating film over the exposed portion of said active layer;

forming a gate wiring and a second capacitance electrode over said insulating film containing silicon and said first insulating film;

forming a first interlayer insulating film over said gate wiring and said second capacitance electrode;

exposing a portion of said second capacitance electrode by removing a part of said first interlayer insulating film;

forming a second dielectric over the exposed portion of said second capacitance electrode;

forming a light-shielding film over said first interlayer insulating film and said second dielectric;

forming a second interlayer insulating film over said light-shielding film;

forming a source wiring or a drain wiring over said second interlayer insulating film;

forming a third interlayer insulating film over said source wiring or said drain wiring; and

forming a pixel electrode, over said third interlayer insulating film, electrically connected with said light-shielding film and said drain wiring.

2. A method according to claim 1, wherein at least one of said first dielectric and said second dielectric is an insulating film formed by a thermal CVD method and containing silicon.

3. A method according to claim 14, wherein said pixel electrode is an anode or a cathode of an EL element.