Method for fabricating and identifying integrated circuits and self-identifying integrated circuits
First Claim
1. A method for fabricating a plurality of topologically different integrated circuits, said method comprising:
- (a) fabricating a plurality of first integrated circuits, each first integrated circuit comprising N vertically stacked device layers L1, L2, . . . LN with a first set of photolithographic masks M1, M2 . . . MMAX;
(b) fabricating a plurality of second integrated circuits, each second integrated circuit comprising M vertically stacked device layers L1, L2, . . . LM, where M<
N, with a second set of photolithographic masks, wherein all of the photolithographic masks of the second set of masks used to form device layers L1, L2, . . . LM−
1 in (b) are included in the first set of masks used in (a).
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Accused Products
Abstract
Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.
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Citations
17 Claims
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1. A method for fabricating a plurality of topologically different integrated circuits, said method comprising:
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(a) fabricating a plurality of first integrated circuits, each first integrated circuit comprising N vertically stacked device layers L1, L2, . . . LN with a first set of photolithographic masks M1, M2 . . . MMAX;
(b) fabricating a plurality of second integrated circuits, each second integrated circuit comprising M vertically stacked device layers L1, L2, . . . LM, where M<
N, with a second set of photolithographic masks, wherein all of the photolithographic masks of the second set of masks used to form device layers L1, L2, . . . LM−
1 in (b) are included in the first set of masks used in (a). - View Dependent Claims (2, 3, 4, 5)
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6. A method for fabricating a plurality of topologically different integrated circuits, said method comprising:
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(a) fabricating a plurality of first three-dimensional memory arrays, each first three-dimensional memory array having 2j vertically stacked memory cell layers L1, L2, . . . L2j, with a first set of photolithographic masks M1, M2 . . . MMAX;
(b) fabricating a plurality of second three-dimensional memory arrays, each second three-dimensional memory array having 2k vertically stacked memory cell layers L1, L2, . . . L2k, with a second set of photolithographic masks, wherein k<
j, and wherein all of the photolithographic masks used to form memory cell layers L1, L2, . . . L2k−
1 in (b) are included in the first set of masks used in (a). - View Dependent Claims (7, 8)
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9. A method for identifying a circuit, said method comprising:
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(a) providing a plurality of integrated circuits, each integrated circuit comprising a plurality of vertically stacked device layers, a source, a sensing contact, and a conductive path extending across at least some of the stacked device layers, said integrated circuits comprising first ones of the integrated circuits, in which the conductive path interconnects the respective sensing contact and source, and second ones of the integrated circuits, in which the conductive path does not interconnect the respective sensing contact and source;
(b) supplying circuit identification signals selected from a first set with the first integrated circuits in response to sensed signals on the respective sensing contacts within a first range of values; and
(c) supplying circuit identification signals selected from a second set with the second integrated circuits in response to sensed signals on the respective sensing contacts within a second range of values. - View Dependent Claims (10, 11, 12)
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13. A self-identifying circuit comprising:
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an integrated circuit comprising a plurality of vertically stacked device layers, a source, a sensing contact, and a conductive path coupled with the sensing contact and extending across at least some of the stacked device layers, a parameter on the sensing contact indicative of whether the conductive path extends continuously between the sensing contact and the source;
a memory storing first and second sets of integrated circuit identification signals;
a switch responsive to the sensing contract, coupled with the memory, and operative (1) to select a circuit identification signal from the first set as an output when a sensed signal on the sensing contact is in a first range of values, and (2) to select a circuit identification signal from the second set as the output when the sensed signal on the sensing contact is in a second range of values. - View Dependent Claims (14, 15, 16, 17)
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Specification