Method for fabricating and identifying integrated circuits and self-identifying integrated circuits

• US 20040029357A1
• Filed: 08/06/2003
• Published: 02/12/2004
• Est. Priority Date: 02/04/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Vyvoda, Michael A., Crowley, Matthew P.
• Granted Patent: US 6,947,305 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Claims

1. A method for fabricating a plurality of topologically different integrated circuits, said method comprising:

(a) fabricating a plurality of first integrated circuits, each first integrated circuit comprising N vertically stacked device layers L₁, L₂, . . . L_N with a first set of photolithographic masks M₁, M₂ . . . M_MAX;

(b) fabricating a plurality of second integrated circuits, each second integrated circuit comprising M vertically stacked device layers L₁, L₂, . . . L_M, where M<

N, with a second set of photolithographic masks, wherein all of the photolithographic masks of the second set of masks used to form device layers L₁, L₂, . . . L<sub>M−

1</sub> in (b) are included in the first set of masks used in (a).

2. The method of claim 1 wherein the first and second integrated circuits comprise respective three-dimensional memory arrays, and wherein the devices of the first and second integrated circuits comprise memory cells.

3. The method of claim 2 wherein each first integrated circuit has 2^j vertically stacked device layers, wherein each second integrated circuit has 2^k vertically stacked device layers, and wherein k<

j.

4. The method of claim 1 wherein the second set of masks includes only masks M₁, M₂ . . . . M_L, wherein L<

MAX.

5. The method of claim 1 wherein all of the photolithographic masks of the second set of masks used in (b) are included in the first set of masks used in (a).

6. A method for fabricating a plurality of topologically different integrated circuits, said method comprising:

(a) fabricating a plurality of first three-dimensional memory arrays, each first three-dimensional memory array having 2^j vertically stacked memory cell layers L₁, L₂, . . . L₂^j, with a first set of photolithographic masks M₁, M₂ . . . M_MAX;

(b) fabricating a plurality of second three-dimensional memory arrays, each second three-dimensional memory array having 2^k vertically stacked memory cell layers L₁, L₂, . . . L₂k, with a second set of photolithographic masks, wherein k<

j, and wherein all of the photolithographic masks used to form memory cell layers L₁, L₂, . . . L₂^k<sub>−

1</sub> in (b) are included in the first set of masks used in (a).

7. The method of claim 6 wherein j=3 and k=2.

8. The method of claim 6 wherein all of the photolithographic masks used in (b) are included in the first set of masks used in (a).

9. A method for identifying a circuit, said method comprising:

(a) providing a plurality of integrated circuits, each integrated circuit comprising a plurality of vertically stacked device layers, a source, a sensing contact, and a conductive path extending across at least some of the stacked device layers, said integrated circuits comprising first ones of the integrated circuits, in which the conductive path interconnects the respective sensing contact and source, and second ones of the integrated circuits, in which the conductive path does not interconnect the respective sensing contact and source;

(b) supplying circuit identification signals selected from a first set with the first integrated circuits in response to sensed signals on the respective sensing contacts within a first range of values; and

(c) supplying circuit identification signals selected from a second set with the second integrated circuits in response to sensed signals on the respective sensing contacts within a second range of values.

10. The method of claim 9 wherein the source is characterized by a source value, and wherein the source value is closer to the first range values than to the second layer of values.

11. The method of claim 9 wherein the source and the sensing contact are disposed on different ones of the stacked device layers.

12. The method of claim 9 wherein the source comprises a voltage source, wherein the sensed signal comprises a voltage signal, and wherein the first and second ranges of values are respective ranges of voltages.

13. A self-identifying circuit comprising:

an integrated circuit comprising a plurality of vertically stacked device layers, a source, a sensing contact, and a conductive path coupled with the sensing contact and extending across at least some of the stacked device layers, a parameter on the sensing contact indicative of whether the conductive path extends continuously between the sensing contact and the source;

a memory storing first and second sets of integrated circuit identification signals;

a switch responsive to the sensing contract, coupled with the memory, and operative (1) to select a circuit identification signal from the first set as an output when a sensed signal on the sensing contact is in a first range of values, and (2) to select a circuit identification signal from the second set as the output when the sensed signal on the sensing contact is in a second range of values.

14. The invention of claim 13 wherein the source is characterized by a source value, and wherein the source value is closer to the first range of values than to the second range of values.

15. The invention of claim 13 wherein the source and the sensing contact are disposed on different ones of the stacked device layers.

16. The invention of claim 13 wherein the source comprises a voltage source, wherein the sensed signal comprises a voltage signal, and wherein the first and second ranges of values are respective ranges of voltages.

17. The invention of claim 13 wherein the switch comprises a multiplexer.