High performance system-on-chip passive device using post passivation process

• US 20040029404A1
• Filed: 05/27/2003
• Published: 02/12/2004
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 7,531,417 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A post passivation system, comprising:

a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; and

a passive device, formed over said passivation layer and connected to said at least one top level metal contact point;

wherein said passivation opening'"'"'s width is larger than about 0.1 um.

2. The system of claim 1 further comprising a polymer layer formed over said passivation layer and under said passive device.

3. The system of claim 2 wherein said polymer layer has at least one polymer opening, wherein said polymer opening is aligned with said passivation opening.

4. The system of claim 3 wherein said polymer opening is larger than said passivation opening.

5. The system of claim 4, wherein said passive device is connected to one or more of said top level metal contact points through said polymer opening and said passivation opening.

6. The system of claim 5, wherein metal used to form said passive device and to connect said passive device to said one or more of said top level metal contact points completely covers sidewalls of said polymer opening.

7. The system of claim 5, wherein metal used to form said passive device and to connect said passive device to said one or more of said top level metal contact points only partially covers sidewalls of said polymer opening.

8. The system of claim 2 wherein said polymer layer comprises polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.

9. The system of claim 1, wherein said passive device is a capacitor.

10. The system of claim 9 further comprising metal interconnections, formed of a same material as conductive plates of said capacitor and formed over said passivation layer, and connected to at least one of said top level metal contact points.

11. The system of claim 10 wherein said metal interconnections and said conductive plates are formed of a bottom glue/barrier layer, a seed layer over said bottom glue/barrier layer, and a bulk layer over said seed layer.

12. The system of claim 11 wherein said bottom glue/barrier layer is TiW, said seed layer is Au, and said bulk layer is Au.

13. The system of claim 11 wherein said bottom glue/barrier layer is Cr or Ti, said seed layer is Cu, and said bulk layer is Cu.

14. The system of claim 13 further comprising a cap layer of Ni formed over said bulk layer of Cu.

15. The system of claim 1 wherein said passive device has first and second terminals, said first and second terminals each being connected downward to one of said top level metal contact points.

16. The system of claim 15, wherein said passive device is a capacitor, said capacitor has bottom and top plates, with a dielectric layer between said bottom and top plates, wherein one of said first and second terminals connected to one of said bottom and top plates, and wherein another of said first and second terminals is connected to another of said bottom and top plates.

17. The system of claim 1 further comprising a protective layer of polymer formed over said passive device and over said passivation layer.

18. The system of claim 17 wherein said passive device has first and second terminals, said first terminal being connected to one of said top level metal contact points, and said second terminal exposed through said protective layer of polymer.

19. The system of claim 18 further comprising a solder bump, solder ball, or wire bond pad connected to said second terminal.

20. The system of claim 18, wherein said passive device is a capacitor, said capacitor has bottom and top plates, with a dielectric layer between said bottom and top plates, one of said first and second terminals connected to one of said bottom and top plates, and another of said first and second terminals connected to another of said bottom and top plates.

21. The system of claim 9, wherein said capacitor is formed of bottom and top plates, with a dielectric layer between said bottom and top plates.

22. The system of claim 21, wherein said dielectric layer is Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON.

23. The system of claim 21, wherein said dielectric layer is a polymer, and wherein said polymer is polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.

24. The system of claim 21 further comprising a first polymer layer formed over said passivation layer and under said capacitor.

25. The system of claim 24 wherein said first polymer layer has at least one first polymer opening, wherein said first polymer opening is aligned with said passivation opening.

26. The system of claim 25 wherein said first polymer opening is larger than said passivation opening.

27. The system of claim 25 wherein said first polymer opening is smaller than said passivation opening.

28. The system of claim 26 wherein said dielectric layer has a dielectric layer opening aligning with said passivation opening, wherein said dielectric layer opening is larger than said first polymer opening.

29. The system of claim 27 wherein said dielectric layer has a second polymer opening aligning with said passivation opening, wherein said dielectric layer opening is smaller than said first polymer opening.

30. The system of claim 2, wherein said polymer layer is formed only under passive device, to form polymer islands, thereby reducing stress in said polymer layer.

31. The system of claim 1, wherein said passive device is a resistor.

32. The system of claim 31, wherein said resistor is formed of TaN, NiCr, NiSn, tungsten (W), TiW, TiN, Cr, Ti, TaSi or Ni.

33. The system of claim 32 further comprising metal interconnections, formed of a different material than said resistor, formed over said passivation layer, and connected to at least one of said top level metal contact points.

34. The system of claim 33 wherein said metal interconnections are formed of a bottom glue/barrier layer, a seed layer over said bottom glue/barrier layer, and a bulk layer over said seed layer.

35. The system of claim 32 wherein said bottom glue/barrier layer is TiW, said seed layer is Au, and said bulk layer is Au.

36. The system of claim 33 wherein said bottom glue/barrier layer is Cr or Ti, said seed layer is Cu, and said bulk layer is Cu.

37. The system of claim 36 wherein said resistor has first and second terminals, said first and second terminals each being connected downward to one of said top level metal contact points.

38. The system of claim 31 further comprising a protective layer of polymer formed over said resistor and over said passivation layer.

39. The system of claim 38 wherein said resistor has first and second terminals, said first terminal being connected to one of said top level metal contact points, and said second terminal exposed through said protective layer of polymer.

40. The system of claim 37 further comprising a solder bump, solder ball, or wire bond pad connected to said second terminal.

41. The system of claim 31 further comprising a first polymer layer formed over said passivation layer and under said resistor.

42. The system of claim 41 wherein said first polymer layer has at least one first polymer opening, wherein said first polymer opening is aligned with said passivation opening.

43. The system of claim 42 wherein said first polymer opening is larger than said passivation opening.

44. The system of claim 43 wherein said first polymer opening is smaller than said passivation opening.

45. The system of claim 41, wherein said polymer layer is formed only under said resistor, to form polymer islands, thereby reducing stress in said polymer layer.

46. A post passivation system, comprising:

a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;

a passive device, formed over said passivation layer;

metal interconnections, formed of a same material as said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;

wherein said passivation opening'"'"'s width is larger than about 0.1 um.

47. The system of claim 46 wherein said passive device is a capacitor.

48. The system of claim 47 further comprising a protective layer of polymer formed over said capacitor and over said passivation layer.

49. The system of claim 48 wherein said capacitor has first and second terminals, said first and second terminals exposed through said protective layer of polymer.

50. The system of claim 49 further comprising a solder bump, solder ball, or wire bond pad connected to said first and second terminals.

51. The system of claim 46 wherein said capacitor has top and bottom plates, and a dielectric layer between said top and bottom plates.

52. The system of claim 51, wherein said dielectric layer is Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON.

53. The system of claim 51, wherein said dielectric layer is a polymer, and wherein said polymer is polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.

54. A post passivation system, comprising:

a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;

a passive device, formed over said passivation layer;

metal interconnections, formed of a different material than said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;

wherein said passivation opening'"'"'s width is larger than about 0.1 um.

55. The system of claim 54 wherein said passive device is a resistor.

56. The system of claim 54 further comprising a protective layer of polymer formed over said resistor and over said passivation layer.

57. The system of claim 55 wherein said resistor has first and second terminals, said first and second terminals exposed through said protective layer of polymer.

58. The system of claim 57 further comprising a solder bump, solder ball, or wire bond pad connected to said first and second terminals.

59. A method of forming a post passivation system, comprising:

providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; and

forming a passive device, formed over said passivation layer and connected to said at least one top level metal contact point;

wherein said at least one passivation opening is formed to a width larger than about 0.1 um.

60. The method of claim 59 further comprising forming a polymer layer over said passivation layer and under said passive device.

61. The method of claim 60 wherein said polymer layer has at least one polymer opening, wherein said polymer opening is aligned with said passivation opening.

62. The method of claim 61 wherein said polymer opening is formed larger than said passivation opening.

63. The method of claim 60, wherein said passive device is connected to one or more of said top level metal contact points through said polymer opening and said passivation opening.

64. The method of claim 61, wherein metal used to form said passive device and to connect said passive device to said one or more of said top level metal contact points is formed to completely cover sidewalls of said polymer opening.

65. The method of claim 63, wherein metal used to form said passive device and to connect said passive device to said one or more of said top level metal contact points is formed to only partially cover sidewalls of said polymer opening.

66. The method of claim 60 wherein said polymer layer comprises polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.

67. The method of claim 60 wherein said polymer layer is deposited by spin coating.

68. The method of claim 60 wherein said polymer layer is deposited by screen printing.

69. The method of claim 60 wherein said polymer layer is deposited by laminating a dry film of said polymer.

70. The method of claim 59 wherein said passive device is a capacitor.

71. The method of claim 70 further comprising forming metal interconnections, of a same material as said capacitor and formed over said passivation layer, and connected to at least one of said top level metal contact points.

72. The method of claim 71 wherein said metal interconnections and said capacitor are formed by:

forming a polymer layer over said passivation layer; and

forming at least one polymer opening in said polymer layer, wherein said polymer opening is aligned with said passivation opening, wherein said at least one polymer opening is formed larger than said passivation opening.

73. The method of claim 72 further comprising the steps of:

forming a glue/barrier layer in said at least one passivation opening, in said at least one polymer opening, and over said polymer layer;

forming a seed layer over said bottom glue/barrier layer; and

forming a bulk layer over said seed layer.

74. The method of claim 73 wherein said bottom glue/barrier layer is TiW, said seed layer is Au, and said bulk layer is Au.

75. The method of claim 74, wherein said bottom glue/barrier of TiW is formed by sputtering, to a thickness of between about 500 and 5000 Angstroms.

76. The method of claim 74, wherein said seed layer of Au is formed by sputtering, to a thickness of between about 300 and 3000 Angstroms.

77. The method of claim 74, wherein said bulk layer of Au is formed by electroplating, to a thickness of between about 1 and 20 um.

78. The method of claim 73 wherein said bottom glue/barrier layer is Cr or Ti, said seed layer is Cu, and said bulk layer is Cu.

79. The method of claim 78, wherein said bottom glue/barrier of Cr or Ti is formed by sputtering, to a thickness of between about 200 and 1500 Angstroms

80. The method of claim 78, wherein said seed layer of Cu is formed by sputtering, to a thickness of between about 2000 and 10000 Angstroms.

81. The method of claim 78, wherein said bulk layer of Cu is formed by electroplating, to a thickness of between about 2 and 20 μ

m.

82. The method of claim 78 further comprising forming a cap layer of Ni formed over said bulk layer of Cu.

83. The method of claim 82 wherein said cap layer of Ni is formed to a thickness of between about 0.1 and 3 um.

84. The method of claim 59 wherein said passive device has first and second terminals, said first and second terminals each being connected downward to one of said top level metal contact points.

85. The method of claim 59 further comprising forming a protective layer of polymer over said passive device and over said passivation layer.

86. The method of claim 85 wherein said passive device has first and second terminals, said first terminal being connected to one of said top level metal contact points, and said second terminal exposed through said protective layer of polymer.

87. The method of claim 86 further comprising forming a solder bump, solder ball, or wire bond pad connected to said second terminal.

88. The method of claim 70, wherein said capacitor is formed of bottom and top plates, with a dielectric layer between said bottom and top plates.

89. The method of claim 88, wherein said dielectric layer is formed of Si₃N₄, TEOS, Ta₂O₅, TiO₂, SrTiO₃, or SiON.

90. The system of claim 88, wherein said dielectric layer is a polymer, and wherein said polymer is polyimide, benzocyclobutene (BCB), parylene or an epoxy-based material.

91. The method of claim 88 further comprising forming a first polymer layer formed over said passivation layer and under said capacitor.

92. The method of claim 90 wherein said first polymer layer has at least one first polymer opening, wherein said first polymer opening is aligned with said passivation opening.

93. The method of claim 91 wherein said first polymer opening is larger than said passivation opening.

94. The method of claim 92 wherein said first polymer opening is smaller than said passivation opening.

95. The method of claim 93 wherein said dielectric layer has a dielectric layer opening aligning with said passivation opening, wherein said dielectric layer opening is larger than said first polymer opening.

96. The method of claim 94 wherein said dielectric layer has a dielectric layer opening aligning with said passivation opening, wherein said dielectric layer opening is smaller than said first polymer opening.

97. The method of claim 59 wherein said passive device is a resistor.

98. The method of claim 97 further comprising forming metal interconnections, of a different material from said resistor, formed over said passivation layer, and connected to at least one of said top level metal contact points.

99. The method of claim 98 wherein said metal interconnections are formed by:

forming a polymer layer over said passivation layer; and

forming at least one polymer opening in said polymer layer, wherein said polymer opening is aligned with said passivation opening, wherein said at least one polymer opening is formed larger than said passivation opening.

100. The method of claim 99 further comprising the steps of:

forming a glue/barrier layer in said at least one passivation opening, in said at least one polymer opening, and over said polymer layer;

forming a seed layer over said bottom glue/barrier layer; and

forming a bulk layer over said seed layer.

101. The method of claim 100 wherein said bottom glue/barrier layer is TiW, said seed layer is Au, and said bulk layer is Au.

102. The method of claim 101, wherein said bottom glue/barrier of TiW is formed by sputtering, to a thickness of between about 500 and 5000 Angstroms.

103. The method of claim 101, wherein said seed layer of Au is formed by sputtering, to a thickness of between about 300 and 3000 Angstroms.

104. The method of claim 101, wherein said bulk layer of Au is formed by electroplating, to a thickness of between about 1 and 20 um.

105. The method of claim 100 wherein said bottom glue/barrier layer is Cr or Ti, said seed layer is Cu, and said bulk layer is Cu.

106. The method of claim 105, wherein said bottom glue/barrier of Cr or Ti is formed by sputtering, to a thickness of between about 200 and 1500 Angstroms.

107. The method of claim 105, wherein said seed layer of Cu is formed by sputtering, to a thickness of between about 2000 and 10000 Angstroms.

108. The method of claim 105, wherein said bulk layer of Cu is formed by electroplating, to a thickness of between about 2 and 20 μ

m.

109. The method of claim 105 further comprising forming a cap layer of Ni formed over said bulk layer of Cu.

110. The method of claim 109 wherein said cap layer of Ni is formed to a thickness of between about 0.1 and 3 um.

111. The method of claim 97 wherein said resistor has first and second terminals, said first and second terminals each being connected downward to one of said top level metal contact points.

112. The method of claim 97 further comprising forming a protective layer of polymer over said resistor and over said passivation layer.

113. The method of claim 112 wherein said resistor has first and second terminals, said first terminal being connected to one of said top level metal contact points, and said second terminal exposed through said protective layer of polymer.

114. The method of claim 113 further comprising forming a solder bump, solder ball, or wire bond pad connected to said second terminal.

115. The method of claim 97, wherein said resistor is formed of TaN, NiCr, NiSn, tungsten (W), TiW, TiN, Cr, Ti, TaSi or Ni.

127. The method of claim 59, wherein said polymer layer is formed only under passive device, to form polymer islands, thereby reducing stress in said polymer layer.

116. A method of forming a post passivation system, comprising:

providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;

forming a passive device over said passivation layer;

forming metal interconnections, formed of a same material as said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;

wherein said passivation opening'"'"'s width is larger than about 0.1 um.

117. The method of claim 116 wherein said passive device is a capacitor.

118. The method of claim 117 further comprising forming a protective layer of polymer formed over said capacitor and over said passivation layer.

119. The method of claim 118 wherein said capacitor has first and second terminals, said first and second terminals exposed through said protective layer of polymer.

120. The system of claim 119, wherein said capacitor has bottom and top plates, with a dielectric layer between said bottom and top plates, wherein one of said first and second terminals connected to one of said bottom and top plates, and wherein another of said first and second terminals is connected to another of said bottom and top plates.

121. The method of claim 119 further comprising a solder bump, solder ball, or wire bond pad connected to said first and second terminals.

122. The method of claim 116 wherein said capacitor has top and bottom plates, and a dielectric layer between said top and bottom plates.

123. A method of forming a post passivation system, comprising:

providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;

forming a resistor over said passivation layer;

forming metal interconnections, formed of a different material as said resistor and formed over said passivation layer, and connected to at least one of said top level metal contact points;

wherein said passivation opening'"'"'s width is larger than about 0.1 um.

124. The method of claim 123 further comprising forming a protective layer of polymer formed over said resistor and over said passivation layer.

125. The method of claim 124 wherein said resistor has first and second terminals, said first and second terminals exposed through said protective layer of polymer.

126. The method of claim 125 further comprising a solder bump, solder ball, or wire bond pad connected to said first and second terminals.