High performance IP processor
First Claim
1. An IP processor for enabling TCP or SCTP, or UDP, or other session oriented protocols over IP networks, said IP processor comprising:
- a. at least one packet processor for processing IP packets;
b. a session memory for storing IP session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at least one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.
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Accused Products
Abstract
An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol Layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
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Citations
44 Claims
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1. An IP processor for enabling TCP or SCTP, or UDP, or other session oriented protocols over IP networks, said IP processor comprising:
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a. at least one packet processor for processing IP packets;
b. a session memory for storing IP session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at least one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.
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2. The IP processor of claim 2 further comprising at least one of:
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a. an IP Storage session memory for storing IP Storage session information;
b. a classification processor for classifying IP packets;
c. a flow controller for controlling data flow;
d. a policy processor for applying policies;
e. a security processor for performing security operations;
f. a packet memory for storing packets g. a controller for control plane processing;
h. a packet scheduler;
i. a connection manager or session controller for managing sessions;
orj. a combination of any of the foregoing.
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3. In a hardware processor for transporting data packets in TCP/IP or other session oriented IP Protocol sessions or flows over an IP network, a scheduler for scheduling said packets to execution resources of the hardware processor, said scheduler comprising:
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a. a resource allocation table for storing i. the identification of at least some of said execution resources, ii. the identification of the session which at least one of said resources is executing, and iii. the processing state of said resources, and b. a state controller and sequencer coupled to said resource allocation table and to said execution resources, said state controller and sequencer scheduling packets to be processed on a specific session to the execution resource executing said specific session, said scheduling based on at least the execution state of said execution resource. - View Dependent Claims (4, 5)
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6. In a data processing apparatus for transporting data packets in TCP/IP or other session oriented IP Protocol sessions or flows over an IP network, a scheduler for scheduling said packets to execution resources of the data processing apparatus, said scheduler comprising:
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a. a resource allocation table for storing i. the identification of at least some of said execution resources, ii. the identification of the session which at least one of said resources is executing, and iii. the processing state of said resources; and
b. a state controller and sequencer coupled to said resource allocation table, and to said execution resources, said state controller and sequencer scheduling packets to be processed on a specific session to the execution resource executing said specific session, said scheduling based on at least the execution state of said execution resource. - View Dependent Claims (7, 8)
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9. A processor for processing Internet data packets in one or more sessions, and a session memory for storing session information for a plurality of said sessions.
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10. The process, in a hardware implemented control plane processor or session controller coupled to a host processor or a remote peer, of creating new sessions and their corresponding session database entries responsive to new session connection requests received either from the host processor or the remote peer.
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11. The process, in a hardware implemented control plane processor or session controller coupled to a host processor or a remote peer and including a TCP/IP hardware processor engine or an IP storage processor engine, or a combination of any of the foregoing, of tearing down or removing sessions and their corresponding session database entries responsive to session connection closure requests received either from the host processor or the remote peer or as a result of the operation by the said TCP/IP processor engine or IP Storage processor engine or a combination of any of the foregoing.
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12. For use in a hardware implemented IP network application processor including an input queue and queue controller for accepting incoming data packets including new commands from multiple input ports and queuing them on an input packet queue for scheduling and further processing, the process comprising:
- accepting incoming data packets from one or more input ports and queuing them on an input packet queue; and
de-queuing said packets for scheduling and further packet processing.
- accepting incoming data packets from one or more input ports and queuing them on an input packet queue; and
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13. For use in a hardware implemented IP network application processor having one or more output queues for accepting outgoing data packets, including new commands, from one or more packet processor engines, TCP/IP processor engines or IP Storage processing engines, directing said packets on to an output port interface for sending them out to a network interface, said interface sending said packets on to the network, through one or more output packets, said process including:
- accepting incoming data packets from one or more packet processing engines and queuing them on said output packet queue; and
de-queuing said packets for delivery to said output port based on the destination port information in said packet.
- accepting incoming data packets from one or more packet processing engines and queuing them on said output packet queue; and
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14. A hardware implemented IP network application processor for providing TCP/IP operations in sessions on information packets from or to an initiator and providing information packets to or from a target, comprising the combination of:
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a. data processing resources including at least one programmable packet processor for processing said packets;
b. a TCP/IP session cache and memory controller for keeping track of the progress of, and memory useful in, said operations on said packets;
c. a host interface controller capable of controlling an interface to a host computer in an initiator or target computer system or a fabric interface controller capable of controlling an interface to a fabric; and
d. a media independent interface capable of controlling an interface to the network media in an initiator or target.
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15. A hardware processor for enabling Internet Protocol packets or their payloads to stream from a network interface through said hardware processor to a host interface or a fabric interface during packet processing, said hardware processor comprising:
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a. at least one packet processor for processing said packets;
b. a packet memory;
c. a scheduler coupled to said at least one packet processor and to said packet memory for scheduling said packets to said at least one packet processor;
d. a session memory for storing session information for those packets transmitted, encapsulated or encoded using a session oriented protocol; and
e. a session manager coupled to the foregoing elements for managing session states for those packets transmitted, encapsulated or encoded using a session oriented protocol. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. An IP processor for enabling TCP or other session oriented protocols over IP networks, said processor comprising:
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a. at least one packet processor for processing IP packets;
b. a session memory for storing IP session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at lest one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric;
i. wherein said processor operates in multiple stages, including one or more of the stages of (1) receiving incoming IP packets;
(2) providing security for said incoming IP packets;
(3) classifying said incoming IP packets;
(4) scheduling IP packets for processing;
(5) executing data processing operations on IP Packets;
(6) providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;
(7) transmitting IP packets onto a network;
(8) executing packet processing operations on data or commands forming IP packets; and
(9) providing security for outgoing IP packets, and(a) each of said stages is capable of operating on different IP packets concurrently.
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23. A TCP/IP processor implemented in hardware, said processor including a session memory for storing session information for a plurality of sessions.
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24. A TCP/IP processor engine for processing Internet Protocol packets and comprising at least one of each of:
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a. a checksum hardware for performing checksum operations;
b. a data memory for storing data used in the TCP/IP processor engine;
c. an instruction memory for storing instructions used in the TCP/IP processor engine;
d. an instruction fetch mechanism for fetching said instructions;
e. an instruction decoder for decoding said instructions;
f. an instruction sequencer for sequencing said instructions;
g. a session database memory for storing TCP/IP session data;
orh. a session database memory controller for controlling said session database memory;
or a combination of any of the foregoing items a through i; and
a host interface, or a fabric interface, or bus controller, or memory controller or combination of any of the foregoing for coupling to host or a fabric.
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26. A TCP/ IP processor for enabling TCP, SCTP, or UDP or other session oriented protocols, over IP networks, said processor comprising:
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a. at least one TCP/IP processor engine for processing IP packets;
b. a session memory for storing session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at lest one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric. - View Dependent Claims (27)
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28. A host processor having a SCSI command layer and an iSCSI or IP Storage driver, said host processor capable of being coupled to a hardware implemented iSCSI or IP Storage controller useable in high speed storage over IP, said controller for transporting received iSCSI or IP Storage commands and PDUs, said controller having access to a data base for keeping track of data processing operations, said database being in memory on said controller, or in memory partly on said controller and partly in a computing apparatus other than said controller, said controller having a transmit and a receive path for data flow, said controller comprising:
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a. a command scheduler for scheduling processing of commands, said scheduler coupled to said SCSI command layer and to said iSCSI or IP Storage driver;
b. a receive path for data flow of received data and a transmit path for data flow of transmitted data;
c. at least one transmit engine for transmitting iSCSI or IP Storage PDUs;
d. at least one transmit command engine for interpreting said PDUs and performing operations including retrieving information from said host processor using remote direct memory access and keeping command flow information in said database updated as said retrieving progresses;
e. at least one receive command engine; and
f. at least one receive engine for interpreting received commands into requests for at least one of said at least one receive command engine.
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29. An IP storage processor implemented in hardware, said processor including a session memory for storing session information for a plurality of sessions.
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30. An IP storage processor engine for processing Internet Protocol packets and comprising at least one of each of:
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a. CRC hardware for performing CRC functions;
b. a data memory for storing data used in the processor engine;
c. an instruction memory for storing instructions used in the processor engine;
d. an instruction fetch mechanism for fetching said instructions;
e. an instruction decoder for decoding said instructions;
f. an instruction sequencer for sequencing said instructions;
g. an IP storage session database memory for storing IP storage session information;
h. an IP storage session database memory controller for controlling said IP storage session database memory;
i. combination of any of the foregoing items a through j; and
j. a host interface, or a fabric interface, or bus controller, or memory controller or combination thereof for coupling to a host or to a fabric. - View Dependent Claims (31)
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32. An IP Storage processor for enabling IP Storage protocols over IP networks, said processor comprising:
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a. at least one IP Storage processor engine for processing IP storage packets;
b. an IP Storage session memory for storing session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at least one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric. - View Dependent Claims (33)
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34. An IP processor capability for enabling TCP or other session oriented protocols over IP networks, said processor comprising:
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a. at least one packet processor for processing IP packets;
b. a session memory for storing IP session information;
c. at least one memory controller for controlling memory accesses;
d. at least one media interface for coupling to at least one network; and
e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric;
i. wherein said processor operates in multiple stages, including one or more of the stages of (1) receiving incoming IP packets;
(2) providing security for processing said incoming IP packets if needed;
(3) classifying said incoming IP packets;
(4) scheduling IP packets for processing;
(5) executing data and/or processing operations on IP Packets;
(6) providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;
(7) executing protocol processing operations on data or commands forming IP packets;
(8) providing processing security for outgoing IP packets, if needed;
or (9) transmitting IP packets onto a network;
or any combination of the foregoing; and
ii. each of said stages is capable of operating on different IP packets concurrently.
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35. The IP processor of claim 35 wherein each stage of said IP processor may take a different length of time to perform its function than one or more of the other stages of said IP processor.
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36. A TCP/IP processor for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said processor comprising:
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a. At least one TCP/IP processor engine for processing IP packets;
b. A session memory for storing session information;
C. At least one memory controller for controlling memory accesses;
d. At least one media interface for coupling to at least one network; and
e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric. - View Dependent Claims (37, 42)
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38. A TCP/IP processor for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said stack providing an interface to sockets layer functions in a host processor to transport data traffic, said processor comprising:
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a. At least one TCP/IP processor engine for processing IP packets;
b. A session memory for storing session information;
c. At least one memory controller for controlling memory accesses;
d. At least one media interface for coupling to at least one network; and
e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric. - View Dependent Claims (39, 43)
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40. An IP Storage processor for enabling IP Storage protocols over IP networks, said processor including an IP Storage stack providing IP Storage protocol termination and origination, transporting information in active sessions over IP networks by transporting PDU'"'"'s specified by the IP storage standard said processor comprising:
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a. At least one IP Storage processor engine for processing IP Storage packets;
b. An IP Storage session memory for storing session information;
c. At least one memory controller for controlling memory accesses;
d. At least one media interface for coupling to at least one network; and
e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric. - View Dependent Claims (25, 41, 44)
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Specification