Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell

• US 20040031975A1
• Filed: 03/17/2003
• Published: 02/19/2004
• Est. Priority Date: 03/18/2002
• Status: Active Grant

• Current Assignee: AmberWave Systems Corporation, Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften e.V. (Max-Planck-Gesellschaft zur Frderung der Wissenschaften e)
• Original Assignee: Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften e.V. (Max-Planck-Gesellschaft zur Frderung der Wissenschaften e)
• Inventors: Burghard, Marko, Kern, Klaus, Cui, Jingbiao
• Granted Patent: US 7,049,625 B2
• Time in Patent Office: Days
• US Class Current: 257/213
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/17 Memory cell being a nanowire transistor
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/701 Organic molecular electronic devices
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Abstract

A field effect transistor memory cell has a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed from at least one nanowire which has at least one defect such that charges can be trapped in the defects and released from the defects by a voltage applied to the gate region. A memory device built up from such memory cells and a method of manufacturing such memory cells is also disclosed.

Claims

1. Field effect transistor memory cell having a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed by at least one nanowire which has at least one defect such that charges can be trapped in and released from the defects by a voltage applied to the gate region.

2. Memory cell in accordance with claim 1, characterized in that the defects forms a quantum well with at least one discrete energy level for one or more charge carriers.

3. Memory cell in accordance with claim 1, characterized in that the or each defect is formed by a metallic region, in particular with an electron continuum, in which at least one charge carrier can be stored in particular by supplying a coulomb charge energy.

4. Memory cell in accordance with claim 1, characterized in that the or each defect is a defect which has arisen during the formation of the at least one nanowire.

5. Memory cell in accordance with claim 1, characterized in that the or each defect is a defect which has arisen after the formation of at least one nanowire.

6. Memory cell in accordance with claim 1, characterized in that the or each defect is a defect induced from the outside.

7. Memory cell in accordance with claim 1, characterized in that the or each defect is a structural defect.

8. Memory cell in accordance with claim 1, characterized in that the or each defect is a chemical defect.

9. Memory cell in accordance with claim 1, characterized in that the or each defect is formed by a temperature treatment of the at least one nanowire in a gas atmosphere.

10. Memory cell in accordance with claim 9, characterized in that the gas atmosphere contains oxygen, nitrogen and/or fluorine.

11. Memory cell in accordance with claim 1, characterized in that the or each defects is formed by bombardment of the at least one nanowire with ions and/or reactive elements and/or compounds.

12. Memory cell in accordance with claim 1, characterized in that the or each defect is electrochemically formed.

13. Memory cell in accordance with claim 1, characterized in that the or each defect is formed by a plurality of atoms, molecules or compounds covalently bonded to the nanowire.

14. Memory cell in accordance with claim 1, characterized in that the or each defect is formed by a chemical group attached to the at least one nanowire.

15. Memory cell in accordance with claim 14, characterized in that the chemical group includes a benzene molecule which is bound by a C—

C—

or a C—

N—

C-bond to the at least one nanowire.

16. Memory cell in accordance with claim 15, characterized in that a substituent is bounded to a benzene molecule which acts as a donor or acceptor or neutral bond.

17. Memory cell in accordance with claim 1, characterized in that the at least one nanowire has one of the following forms:

a solid wire form, a closed tube form, an open tube form or a strip form.

18. Memory cell in accordance with claim 1, characterized in that the at least one nanowire is formed of one of the following materials:

in tube form or in solid wire form of carbon, silicone or a chalcogenide, including tungsten oxide, tungsten selenide, tungsten sulphide, tantalum sulphide, niobium sulphide and in massive wire form of silicon, silicon carbide, indium phosphide or indium arsenide.

19. Semiconductor memory device comprising a plurality of field effect transistor memory cells in accordance with claim 1 which are arranged in a matrix on a carrier substrate.

20. Memory device in accordance with claim 19, characterized in that the nanowires of the individual Memory cells are arranged at least approximately parallel to one another in rows and/or in columns on the carrier substrate.

21. Memory device in accordance with claim 19, characterized in that the nanowires are arranged in grooves on a surface of a single crystal carrier substrate.

22. Memory device in accordance with claim 21, characterized in that the grooves are formed by self organisation of the surface of the single crystal carrier substrate.

23. Memory device in accordance with claim 19, characterized in that for each memory cell discrete source, drain and gate electrodes are provided.

24. Memory device in accordance with claim 20, characterized in that the memory cells of each row or of each column each have discrete drain and gate electrodes but only one common source electrode.

25. Memory device in accordance with claim 23, characterized in that the gate electrodes lie in a column plane with the source and drain electrodes.

26. Memory device in accordance with claim 23, characterized in that the gate electrodes are arranged in a plane beneath or above the plane formed by the nanowires.

27. Memory device in accordance with claim 23, characterized in that the gate electrodes are provided on side surfaces of the grooves, accommodating the nanowires.

28. Memory device in accordance with claim 23, characterized in that the gate electrodes are connected via conductive traces to respective contact regions at the edge of the carrier substrate, for example adjacent to the source and/or drain electrodes.

29. Memory device in accordance with claim 28, characterized in that the conductive traces and the gate electrodes are separated by an insulating layer from the source and/or drain electrodes and nanowires lying below it.

30. Memory device in accordance with claim 19, characterized in that the memory cells are separated from the atmosphere by a protective layer.

31. Method for manufacturing a field effect transistor memory cell or a plurality of memory cells which are to be connected together to form a semiconductor memory device or are already connected together to form a semiconductor memory device, in particular in accordance with claim 1, having at least one nanowire which extends at least after manufacture between a source region and a drain region, characterized in that the or each nanowire is treated so that at least one defect is produced in each case which forms a quantum well having at least one discrete energy level.

32. Method in accordance with claim 31, characterized in that a collection of nanowires, which are at least partly stuck together and form bundles of nanowires, are split up in a solution of a surface active material, in particular of a tenside, at least partly into individual nanowires and are applied with the solution onto the surface of a carrier substrate and then treated for the manufacture of the defects.

33. Method in accordance with claim 31, characterized in that the nanowires, at least some of which have a metallic conductivity and at least some of which have a semiconducting characteristic, are influenced by a thermal treatment, optionally in a gas atmosphere, in such a way that the nanowires with metallic conductivity are converted into semiconducting nanowires and provided with defects.

34. Method in accordance with claim 31, characterized in that the nanowires and/or bundles of nanowires are aligned at least approximately parallel to one another on a surface of a carrier substrate.

35. Method in accordance with claim 31, characterized in that a surface of a carrier substrate is pre-treated in such a way that the nanowires and/or bundles of nanowires arrange themselves in an ordered manner as a result of a self organisation effect and in particular align themselves at least approximately parallel to one another.

36. Method in accordance with claim 31, characterized in that grooves are formed in a surface of a mono-crystalline carrier substrate by a self organisation effect and the nanowires and/or bundles of nanowires are subsequently arranged in the grooves.

37. Method in accordance with claim 31, characterized in that the or each nanowire is produced in a CVD process on a carrier substrate between already present source and drain regions with the simultaneous application of an electrical field between the source and drain regions.

38. Method in accordance with claim 37, characterized in that the or each nanowire is treated following the CVD process or during the CVD process in the same apparatus with chemical elements, molecules or compounds which produce defects.

39. Method in accordance with claim 31, characterized in that the or each defect is produced during the formation of the respective nanowires.

40. Method in accordance with claim 31, characterized in that the or each defect is produced after the formation of the respective nanowire.

41. Method in accordance with claim 31, characterized in that the or each defect is induced from the outside.

42. Method in accordance with claim 31, characterized in that at least one structural defect is produced or induced.

43. Method in accordance with claim 31, characterized in that at least one chemical defect is produced or induced.

44. Method in accordance with claim 43, characterized in that the or each chemical defect is formed by a plurality of atoms, molecules or compounds covalently bound to the nanowire.

45. Method in accordance with claim 31, characterized in that the or each defect is formed by a temperature treatment of the nanowire in a gas atmosphere.

46. Method in accordance with claim 45, characterized in that the or each defect is formed in a gas atmosphere containing oxygen, nitrogen and/or fluorine.

47. Method in accordance with claim 31, characterized in that the or each defect is formed by bombardment of the nanowire with ions and/or reactive elements and/or compounds.

48. Method in accordance with claim 31, characterized in that the or each nanowire is formed in one of the following forms:

in massive wire form, closed tube form, open tube form or strip form.

49. Method in accordance with claim 31, characterized in that the or each nanowire is formed of one of the following materials:

in tube form or massive wire form from carbon, silicon, chalcogenides, in particular tungsten oxide, tungsten selenide, tungsten sulphide, tantalum sulphide, niobium sulphide and in massive wire form of silicone, silicone carbide, indium phosphide and indium arsenide.