Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

• US 20040031987A1
• Filed: 03/19/2003
• Published: 02/19/2004
• Est. Priority Date: 03/19/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Krumrey, Joachim, Hirler, Franz, Rieger, Walter, Henninger, Ralf, Polzl, Martin, Hofer, Heimo
• Granted Patent: US 7,005,351 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.

Claims

1. A method for fabricating a transistor configuration having a trench transistor cell, which comprises:

introducing a trench into a process layer of a semiconductor substrate;

providing a field electrode and a gate electrode in the trench;

electrically insulating the field electrode and the gate electrode from one another and from the process layer; and

forming a drift zone, a channel zone, and a source zone in the process layer;

at least one of the source zone and the channel zone being formed after the introducing of the trench into the semiconductor substrate.

2. The method according to claim 1, which further comprises:

defining a width d_T of the trench;

after the introducing of the trench into the process layer, lining at least a section of the trench with a first dielectric layer; and

disposing the field electrode on the section of the trench lined by the first dielectric layer.

3. The method according to claim 2, wherein:

the trench has a wall;

the disposing of the field electrode is followed by disposing a gate dielectric layer on sections of the wall of the trench and a second dielectric layer at least on the field electrode; and

the providing of the gate electrode in the trench is on the second dielectric layer.

4. The method according to claim 3, wherein:

the second dielectric layer on the field electrode and the gate dielectric layer are in each case provided as oxide layers;

the oxide layer on the field electrode has a thinnest point;

the gate oxide has a thinnest point; and

the disposing of the oxide layer on the field electrode and of the gate oxide includes a processing step making the thinnest point of the oxide layer on the field electrode at least as thick as the thinnest point of the gate oxide.

5. The method according to claim 4, wherein the processing step is performed at least as an HDP process including:

determining a thinnest point of the oxide layer;

depositing the oxide layer with a thinnest point substantially on the field electrode and onto uncovered sections of the first dielectric layer surrounding the field electrode; and

making the thinnest point of the oxide layer at least 5% thicker than the thinnest point of the gate oxide.

6. The method according to claim 5, which further comprises depositing the oxide layer on the field electrode.

7. The method according to claim 4, wherein the processing step includes diffusion-limited depositing of silicon oxide by using tetraethyl orthosilane while applying a thinner-on-average layer thickness of the silicon oxide at the trench walls than on the field electrode.

8. The method according to claim 4, wherein the processing step includes moist oxidating in oxygen and hydrogen to oxidize a material of the field electrode at a higher rate than a material of the trench wall.

9. The method according to claim 5, which further comprises following the process step with a dry oxidation process.

10. The method according to claim 1, which further comprises:

introducing the trench in the process layer by one of implantation, activation, and diffusion;

then forming both the channel zone and the source zone.

11. The method according to claim 1, which further comprises forming at least one of the channel zone and the source zone after the providing of the gate electrode.

12. The method according to claim 1, which further comprises:

defining a wall of the trench;

defining a body height of the trench at a junction of the channel zone and the drift zone in the semiconductor substrate;

forming an interspace between the field electrode and the semiconductor substrate;

after the introducing of the trench, filling the trench virtually completely with a material of the field electrode;

removing the first dielectric layer by etching from sections of the trench wall not covered by the field electrode and also from the interspace as far as the body height of the trench;

applying a second dielectric layer to the field electrode and at least to a section of the trench wall not covered by the field electrode;

subsequently filling the trench with a material of the gate electrode; and

fashioning the gate electrode at a level of the channel zone beside sections of the field electrode.

13. The method according to claim 2, which comprises lining, in sections, the trench with a first dielectric layer by:

defining a substrate surface of the semiconductor substrate;

applying, at least in sections, the first dielectric layer, on the substrate surface patterned by the trench;

applying a first auxiliary layer on the first dielectric layer to completely fill the trench with a material of the first auxiliary layer;

removing sections of the first auxiliary layer, the trench remaining filled as far as the body height by residual sections of the first auxiliary layer;

at least reducing a layer thickness d_dS of the first dielectric layer in sections not covered by the residual sections of the first auxiliary layer; and

removing the residual sections of the first auxiliary layer.

14. The method according to claim 13, which further comprises:

after the removing of the sections of the first auxiliary layer from the trench, providing a second, patterned auxiliary layer in the trench, above the body height, on sections of the trench provided for contact connection of the gate and field electrodes and also on adjoining regions of the substrate surface;

reducing a layer thickness of the first dielectric layer in the sections of the trench covered neither by the residual sections of the auxiliary layer nor by the second auxiliary layer; and

subsequently removing the residual sections of the auxiliary layer and of the second auxiliary layer.

15. The method according to claim 14, wherein the first dielectric layer is removed.

16. The method according to claim 13, which further comprises:

after the removing of the residual sections of the first auxiliary layer, lining the trench completely with the first dielectric layer having a layer thickness d_o in an upper region of the trench extending between the body height and the substrate surface and a layer thickness d_u in a lower region of the trench, where d_u>

d_o; and

the introducing of the field electrode includes the following steps;

defining a width of the trench d_T;

conformally depositing the material of the field electrode with a layer thickness d_A, for which the following holds true;

d_A>

(d_T/2−

d_U) and d_A<

(d_T/2−

d_o); and

isotropicly etching-back the material of the field electrode by at least removing the material completely from the upper region of the trench.

17. The method according to claim 13, which further comprises:

using a photoresist as the material of the first auxiliary layer; and

subjecting the photoresist to a postbake process before the first dielectric layer is removed in sections.

18. The method according to claim 13, which further comprises:

before the applying of the first auxiliary layer, applying an adhesion promoter; and

removing the adhesion promoter before the introducing of the field electrode.

19. The method according to claim 3, which further comprises:

reducing a layer thickness d_dS of the first dielectric layer to a layer thickness d_GD of the gate dielectric layer in sections of a trench wall of the trench covered neither by the first auxiliary layer nor by the field electrode, during the forming of the gate dielectric layer at sections of the trench wall;

disposing the second dielectric layer exclusively on the field electrode; and

forming the gate dielectric layer exclusively by the sections of the first dielectric layer having a reduced thickness.

20. The method according to claim 3, wherein the forming of the gate dielectric layer at sections of the trench wall includes:

reducing a layer thickness d_dS of the first dielectric layer to a reduced layer thickness in sections of the trench wall that are covered neither by an auxiliary layer nor by the field electrode; and

disposing the second dielectric layer on the field electrode and at least in sections of the trench wall not covered by the field electrode; and

forming the gate dielectric from sections of a double layer including the first and the second dielectric layer.

21. The method according to claim 20, which further comprises:

completely removing the first dielectric layer in sections of the trench wall covered neither by an auxiliary layer nor by the field electrode; and

forming the gate dielectric layer exclusively from sections of the second dielectric layer.

22. The method according to claim 3, which further comprises providing at least one of the first and the second dielectric layer in each case at least in sections as a material selected from the group consisting of a thermal oxide, a deposited oxide, a nitride, an oxynitride, and a multilayer structure.

23. The method according to claim 2, which further comprises:

reducing a layer thickness d_dS of the first dielectric layer, in sections not covered by the field electrode;

forming a collar with the first dielectric layer; and

forcing overhanging regions of the field electrode projecting in the trench beyond the collar to recede.

24. The method according to claim 23, which further comprises removing of the first dielectric layer in the sections not covered by the field electrode.

25. The method according to claim 1, which further comprises providing a material of at least one of the field electrode and the gate electrode at least in sections with a highly conductive component.

26. The method according to claim 25, which further comprises using a silicide as the highly conductive component.

27. A trench transistor cell in a substrate, comprising:

a semiconductor substrate having a substrate surface and a trench formed therein, said trench having a trench bottom;

a drain zone, a drift zone, a channel zone, and a source zone formed in said semiconductor substrate in each case successively and in essentially horizontally layered fashion;

a body height defined opposite said drift zone and channel zone and in said semiconductor substrate where said drift zone and said channel zone join;

a first dielectric layer having an upper edge and lining said trench as far as essentially said body height;

a gate oxide disposed between said body height and said substrate surface and having a thinnest point;

a field electrode disposed in said trench and extending essentially from said trench bottom as far as said upper edge of said first dielectric layer;

a gate electrode disposed in said trench between about said body height and said substrate surface;

a second oxide layer disposed in said trench between said gate electrode and said field electrode, said second oxide layer, at every point between said field electrode and said gate electrode, being at least as thick as said thinnest point of said gate oxide.

28. A transistor configuration, comprising a trench transistor cell according to claim 27.