Method of regulating the supply voltage of a load and related voltage regulator

• US 20040032242A1
• Filed: 05/30/2003
• Published: 02/19/2004
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Mariani, Adalberto, Corva, Giulio
• Granted Patent: US 6,894,471 B2
• Time in Patent Office: Days
• US Class Current: 323/284
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

The method is for regulating the supply voltage of a load via a switching voltage regulator having an inductor driven by at least a power switch for delivering current to an output capacitor having a certain parasitic series resistance, connected between the output node of the regulator and ground and to an electric load eventually connected in parallel to the output capacitor. The method includes establishing a reference voltage, generating a comparison signal as the sum of a first voltage signal proportional to the current circulating in the inductor and of a second voltage signal depending on the difference between the output voltage and the reference voltage and on the first voltage signal. The comparison signal is compared with at least a threshold for generating a logic signal that switches between an active state and an inactive state and viceversa each time that the threshold is crossed, and the turn on or the turn off of the switch is controlled as a function of the state of the logic signal.

Claims

1. A method of regulating the supply voltage of a load by a switching voltage regulator having an inductor (L) driven by at least a power switch for delivering current to an output capacitor (C_OUT) with a certain parasitic series resistance (ESR) connected between an output node of the regulator and ground and to an electric load connected in parallel to the capacitor, comprising the steps of

establishing a reference voltage (V′

_REF),

generating a comparison signal (V_COMP) as the sum of a first voltage signal (R_SI_L) proportional to the current circulating in the inductor (L) according to a certain proportionality coefficient (R_S) and of a second voltage signal (V_INT) function of the difference between the output voltage (V_OUT) and said reference voltage (V′

_REF) and of said first voltage signal,

comparing said comparison signal (V_COMP) with at least a threshold for generating a logic signal that switches between an active state and an inactive state and viceversa each time that said threshold is crossed,

commanding the turn on or the turn off of said power switch in function of the state of said logic signal,

characterized in that said second voltage signal (V_INT) is generated by integrating the sum between said first signal and the difference, multiplied by a certain quantity (α

), between the output voltage (V_OUT) of the regulator and said reference voltage (V′

_REF).

2. The method of regulation of claim 1, wherein said logic signal is generated by comparing said comparison signal (V_COMP) with an upper threshold and a lower threshold in a hysteretical mode.

3. The method of claim 1, wherein said certain quantity (α

) is the ratio between said proportionality coefficient (R_S) and the output resistance (R_O) of the regulator under steady state conditions, said integration being carried out with an integration constant (K_INT) equal to the inverse of the product between the capacitance of said output capacitor (C_OUT) and said parasitic series resistance (ESR).

4. A switching voltage regulator comprising an inductor (L) driven by at least a power switch for delivering current to an output capacitor (C_OUT) having a certain parasitic series resistance (ESR) connected between an output node and ground and to an electric load connected in parallel to the capacitor (C_OUT), a logic control circuit of said switch, circuit means for generating a voltage signal proportional to the current flowing in the inductor (L) according to a certain proportionality coefficient (R_S), second circuit means (g_m, R1, R2, C1, V′

_REF) for generating an amplified and filtered error signal (V−

;

V+), and a comparator comparing said amplified and filtered error signal and said voltage signal proportional to the current in the inductor (L) and generating a logic signal applied to an input of the logic control circuit of said power switch,

characterized in that said second circuit means comprise

an integrator (g_m, C_INT, R1, R2) of the sum between said voltage signal and the difference, scaled of a certain quantity (α

), between the output voltage and a reference voltage (V′

_REF).

5. The regulator of claim 4, wherein said first circuit means consist in a sensing resistor (R_S) connected in series to said inductor (L) toward the output node of the regulator.

6. The regulator of claim 4, characterized in that the capacitance of said output capacitor (C_OUT) is greater than the ratio between a maximum admissible variation of the output current (Δ

I_OUT,MAX) and the product between the parasitic series resistance thereof (ESR) and a maximum admissible speed variation of the current flowing in the inductor (m).

7. The regulator of claim 4, characterized in that the capacitance of said output capacitor (C_OUT) is greater than the ratio between a maximum admissible variation of the output current (Δ

I_OUT,MAX) and the product between the output resistance thereof (R_O) of the regulator in steady state conditions and a maximum admissible speed variation of the current flowing in the inductor (m), being said output resistance (R_O) greater than the parasitic series resistance (ESR).

8. The regulator according to claim 4, characterized in that said integrator comprises circuit means capable of preventing that the output thereof exceeds a maximum and a minimum value.

9. The regulator according to claim 4, characterized in that said quantity (α

) is equal to the ratio between said coefficient (R_S) and the output resistance (R_O) of the regulator under steady state conditions, said integrator (g_m, C_INT, R1, R2) having an integration constant (K_INT) equal to the inverse of the product between the capacity of said output capacitor (C_OUT) and said parasitic series resistance (ESR).

10. The regulator of claim 4, wherein said inductor is driven by a half-bridge power stage connected between a not regulated voltage source node and the ground node of the circuit.

11. The regulator of claim 5, characterized in that said integrator (g_m, C_INT, R1, R2) comprises

a resistive voltage divider (R1, R2), constituted by a pair of resistors first (R1) and second (R2), connected between said output node of the regulator and a node at said reference voltage (V′

_REF),

an error amplifier (g_m) having a non inverting input (+) connected to the common node between said inductor (L) and said sensing resistance (R_S) and an inverting input (−

) coupled to the intermediate voltage node between said first resistor (R1) and said second resistor (R2), and

an integration capacitor (C_INT) connected between said non inverting node (+) and an output of said error amplifier (g_m),

said comparator having an inverting input connected to the output of said amplifier and a non inverting input connected to said output node of the regulator.

12. The regulator of claim 5, characterized in that said integrator (g_m, C_INT, R1, R2) comprises

a resistive voltage divider (R1, R2), constituted by a pair of resistors first (R1) and second (R2), connected between said output node of the regulator and a node at said reference voltage (V′

_REF),

an error amplifier (g_m) having an inverting input (−

) connected to the common node between said inductor (L) and said sensing resistance (R_S) and a non inverting input (+) coupled to an intermediate voltage node between said first resistor (R1) and said second resistor (R2), and

an integration capacitor (C_INT) connected between said output node of the regulator and an output of said error amplifier (g_m),

said comparator having an inverting input connected to the common node between said inductor (L) and said sensing resistance (R_S), and a non inverting input connected to the output of said amplifier (g_m).

13. The regulator according to one of claims 11 and 12, characterized in that said comparator is a comparator with hysteresis.

14. The regulator according to one of claims 11 and 12, characterized in that said integrator comprises a clamp (CLAMP) connected in parallel to said integration capacitor (C_INT).

15. The regulator according to one of claims 11 and 12, characterized in that

the ratio between the transconductance of said amplifier (g_m) and the capacitance of said integration capacitor (C_INT) is equal to the inverse of the product between the capacitance of said output capacitor (C_OUT) and the parasitic series resistance (ESR) thereof, and

the ratio between the value of said first resistor (R1) and the total resistance (R1+R2) of said resistive voltage divider is equal to the ratio between said sensing resistance (R_S) and the output resistance (R_O) of the regulator in steady state conditions.

16. The regulator according to one of claims 11 and 12, characterized in that said error amplifier (g_m) is capable of providing a maximum current (I_INT,MAX) greater than the ratio between

the product of said sensing resistance (R_S) by the capacitance of said integration capacitor (C_INT) and by the maximum admissible variation of the output current (Δ

I_OUT,MAX), and

the product between said output resistance (R_O) and the capacitance of said output capacitor (C_OUT).

17. The regulator of claim 14, characterized in that said clamp (CLAMP) has a negative lower intervention threshold.

18. The regulator of claim 14, characterized in that said clamp (CLAMP) has a positive upper intervention threshold.

19. A method of defining a switching voltage regulator comprising an inductor (L) driven by at least a power switch for delivering current to an output capacitor (C_OUT) having a certain parasitic series resistance (ESR), connected between an output node and ground, and to an electrical load connected in parallel to the capacitor (C_OUT), a logic control circuit of said switch, circuit means capable of generating a voltage signal proportional to the current in the inductor (L) according to a certain proportionality coefficient (R_S), second circuit means (g_m, R1, R2, C1, V′

_REF) capable of generating an amplified and filtered error signal (V−

;

V+), and a comparator input with a comparison signal (V_COMP) function (V_COMP=(V_OUT−

V′

_REF)·

B(s)+R_SA(S)I_L) of said amplified and filtered error signal and said voltage signal proportional to the current flowing in the inductor (L) for generating a logic signal applied to an input of said logic control circuit of said power switch, comprising the steps of;

establishing a maximum admissible variation speed (m) of the current flowing in said inductor,

establishing a maximum admissible variation of the output current (Δ

I_OUT,MAX),

establishing a maximum admissible variation of the output voltage (Δ

V_OUT,MAX),

choosing the value of the output resistance (R_O) of the regulator under steady state conditions alternatively between the value given by

 

Δ

V_OUT,MAX/Δ

I_OUT,MAX and the value of said parasitic series resistance (ESR),

choosing the capacitance of the output capacitor (C_OUT) equal to or greater than the ratio Δ

I_OUT,MAX/(m·

R_O,

fixing a certain reference voltage (V′

_REF), with which to compare the output voltage (V_OUT),

determining complex proportionality functions, first (A(s)) and second (B(s)), of said comparison signal (V_COMP) with the current circulating in the inductor (I_L) and the difference between said output voltage (V_OUT) and said reference voltage (V′

_REF), in function of a certain quantity (α

);

$\hspace{1em}<br><br>\{\begin{array}{c}A<br><br>\left(s\right)=\frac{K_{\mathrm{INT}}}{S}+1\\ B<br><br>\left(s\right)=\mathrm{\alpha <br><br>}<br><br>\frac{K_{\mathrm{INT}}}{S}<br><br>\text{\hspace{1em}<br><br>}\end{array}$

being

$K_{\mathrm{INT}}=\frac{1}{\mathrm{ESR}·<br><br>C_{\mathrm{OUT}}}$

 

and said certain quantity (α

) being

$\mathrm{\alpha <br><br>}=\frac{R_s}{R_O}$