Supply voltage comparator

• US 20040032243A1
• Filed: 04/22/2003
• Published: 02/19/2004
• Est. Priority Date: 04/23/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Giovinazzi, Thierry, La Rosa, Francesco, Ganivet, Filipe
• Granted Patent: US 6,812,747 B2
• Time in Patent Office: Days
• US Class Current: 323/316
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H03K 17/302 in field-effect transistor switches

Abstract

A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

Claims

1. Comparator (COMP) arranged to compare a first voltage (V1, Vcc) applicable to a first input of the comparator and a second voltage (V2, Vps) applicable to a second input of the comparator and to deliver to one output of the comparator an output signal (CS) having a first value when the second voltage is higher than the first voltage and a second value when the second voltage is lower than the first voltage, characterised in that it comprises a first (TP1) and a second (TP2) PMOS transistors arranged as current mirrors, the first PMOS transistor (TP1) having its source connected to the first input of the comparator to receive the first voltage (V1, Vcc), the second PMOS transistor (TP2) having its source connected to the second input of the comparator to receive the second voltage (V2, Vps), the output of the comparator being connected to the drain of one of the transistors.

2. Comparator according to claim 1, in which the gates of the first and the second transistors are interconnected.

3. Comparator according to one of claims 1 and 2, in which a transistor (TP1) has its gate linked to its drain and the output of the comparator is linked to the drain of the other transistor (TP2).

4. Comparator according to one of claims 1 to 3, in which the bulk of the first PMOS transistor (TP1) is linked to the source of the first transistor to receive the first voltage and the bulk of the second PMOS transistor (TP2) is linked to the source of the second transistor to receive the second voltage.

5. Comparator according to one of claims 1 to 4, in which the PMOS transistors have gates of the same dimension (W/L).

6. Comparator (COMP) according to one of claims 1 to 5, comprising a first branch comprising the first PMOS transistor in series with a first source of current (TN1, Vref), and a second branch comprising the second PMOS transistor in series with a second source of current (TN2, Vref), the sources of current imposing substantially equal or proportional currents in the first and second branches.

7. Comparator according to claim 6, in which the first branch comprises the first PMOS transistor (TP1) in series with a first NMOS transistor (TN1), the second branch comprises the second PMOS transistor (TP2) in series with a second NMOS transistor (TN2), the drain of the first PMOS transistor (TP1) being linked to the drain of the first NMOS transistor (TN1), the drain of the second PMOS transistor (TP2) being linked to the drain of the second NMOS transistor (TN2), the gates of the first and second NMOS transistors (TN1, TN2) being linked to the output of a reference voltage generator (Vref(I)) imposing substantially equal or proportional currents in each of the branches.

8. Integrated circuit comprising a comparator (COMP) according to one of claims 1 to 7 arranged to compare an external supply voltage (Vcc) of the integrated circuit and an internal supply voltage (Vps) of the integrated circuit.

9. Integrated circuit according to claim 8, comprising a distribution line (20) of the internal supply voltage (Vps) linked firstly to a booster circuit (PMP) and secondly to a receiving terminal (21) of the external supply voltage (V1, Vcc) through a power switch (Td) driven by the output signal (CS) of the comparator (COMP).

10. Integrated circuit according to claim 9, comprising means (REG) for triggering the booster circuit (PMP) when the internal supply voltage (Vps) is lower than a determined threshold (Vmin), so as to maintain the internal supply voltage (Vps) proximate to the threshold (Vmin) when the external supply voltage (Vcc) is too low, the power switch (Tp) being blocked by the comparator (COMP) when the booster circuit is active.

11. Integrated circuit according to claim 10, in which the power switch is a PMOS transistor (Td) receiving the output signal (CS) of the comparator at its gate.

12. Integrated circuit according to one of claims 9 to 11, in which the booster circuit is a charge pump (PMP).

13. Integrated circuit according to claim 10, comprising a memory array (MA) comprising electrically erasable and programmable memory cells (C_i,j,k), and at least one line decoder (RDEC) having a supply terminal connected to the distribution line (20) of the internal supply voltage (Vps).

14. Integrated circuit according to claim 13, in which the determined threshold (Vmin) is higher than or equal to the sum of a memory cell read voltage (Vread) and a MOS transistor threshold voltage (Vt).

15. Integrated circuit according to one of claims 13 and 14, comprising a single booster circuit (PMP) and a regulator (REG) with two modes of operation, to:

during phases of erasing or programming memory cells, take the internal supply voltage (Vps) to a high erasing or programming voltage (Vpp), and

at least during phases of reading memory cells, maintain the internal supply voltage (Vps) proximate to the determined threshold (Vmin) when the external supply voltage (Vcc) is too low.