Inspecting method, semiconductor device, and display

• US 20040032278A1
• Filed: 07/07/2003
• Published: 02/19/2004
• Est. Priority Date: 08/03/2001
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Abe, Hitoshi, Orii, Toshihiko, Ando, Naoki, Akimoto, Osamu
• Granted Patent: US 7,009,418 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A method for testing a semiconductor substrate forming a liquid crystal display device, which method enables a potential change corresponding to a defective condition of pixel cell driving circuits to be detected accurately even when a ratio of pixel capacitance to wiring capacitance is lowered with decrease in size or increase in definition of the liquid crystal display device. The method includes: a charge retaining step for making pixel capacitances connected to a plurality of pixel switches selected from all pixel switches connected to one data line retain charge; and a detecting step for simultaneously detecting the charge retained in a plurality of the pixel capacitances in the charge retaining step from the one data line.

Claims

1. A testing method for testing a semiconductor substrate, said semiconductor substrate being formed with pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data, said method characterized by comprising:

a charge retaining step for making pixel capacitances connected to a plurality of pixel switches selected from all pixel switches connected to one data line retain charge; and

a detecting step for simultaneously detecting the charge retained in a plurality of the pixel capacitances in said charge retaining step from said one data line.

2. A testing method as claimed in claim 1, characterized in that:

said detecting step includes a pixel switch control step for simultaneously turning on the pixel switches connected to the plurality of pixel capacitances that retain the charge in said charge retaining step.

3. A testing method as claimed in claim 2, characterized in that:

said pixel switch control step includes;

a scanning signal output step for outputting a plurality of scanning signals corresponding to different pixel switch control lines in predetermined timing such that an overlapping period in which the plurality of scanning signals are outputted overlapping each other occurs; and

a control step for controlling conduction/non-conduction of scanning signal paths such that the plurality of scanning signals are supplied to the pixel switch control lines only in a predetermined period from a predetermined time in the overlapping period.

4. A semiconductor device characterized by comprising, on a semiconductor substrate:

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines, and for testing, generating a testing scanning signal for simultaneously turning on an arbitrary plurality of pixel switches on one of said data lines; and

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing.

5. A semiconductor device as claimed in claim 4, characterized in that:

said vertical scanning means includes;

a vertical scanning circuit for scanning in the vertical direction by sequentially outputting the scanning signal for turning on said pixel switch to said pixel switch control lines, and in testing, outputting a plurality of scanning signals corresponding to different pixel switch control lines in predetermined timing such that an overlapping period in which the plurality of scanning signals are outputted overlapping each other in one of said data lines occurs; and

a conduction control circuit unit for controlling conduction/non-conduction of scanning signal paths such that said scanning signals are supplied to the pixel switch control lines only within said overlapping period.

6. A semiconductor device as claimed in claim 5, characterized in that:

in testing, said vertical scanning circuit causes said overlapping period by sequentially outputting a scanning signal having a duration longer than a scanning period for turning on one of said pixel switches to said pixel switch control lines; and

said conduction control circuit is an AND circuit that outputs a logical product of the output signal of said vertical scanning circuit and a mask signal for controlling the conduction/non-conduction of said scanning signal paths, said mask signal being supplied from an external terminal in correspondence with said overlapping period.

7. A semiconductor device as claimed in claim 4, characterized in that:

a selecting circuit for alternatively selecting a data line to be connected to an external testing device from a plurality of said data lines is formed on said semiconductor substrate.

8. A display apparatus characterized by comprising:

a semiconductor substrate;

a counter substrate having a common electrode and disposed opposite to the semiconductor substrate; and

a liquid crystal layer interposed between said semiconductor substrate and said counter substrate;

wherein said semiconductor substrate includes;

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines, and for testing, generating a testing scanning signal for simultaneously turning on an arbitrary plurality of pixel switches on one of said data lines; and

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing.

9. A display apparatus as claimed in claim 8, characterized in that:

said vertical scanning means includes;

a vertical scanning circuit for scanning in the vertical direction by sequentially outputting the scanning signal for turning on said pixel switch to said pixel switch control lines, and in testing, outputting a plurality of scanning signals corresponding to different pixel switch control lines in predetermined timing such that an overlapping period in which the plurality of scanning signals are outputted overlapping each other in one of said data lines occurs; and

a conduction control circuit unit for controlling conduction/non-conduction of scanning signal paths such that said scanning signals are supplied to the pixel switch control lines only within said overlapping period.

10. A display apparatus as claimed in claim 8, characterized in that:

a selecting circuit for alternatively selecting a data line to be connected to an external testing device from a plurality of said data lines is formed on said semiconductor substrate.

11. A testing method for testing a semiconductor substrate, said semiconductor substrate being formed with pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data, said method characterized by comprising:

a potential generating step for generating, in a data line, a potential level corresponding to charge retained in said pixel capacitance;

an amplifying step for amplifying the potential level generated in said data line in said potential generating step by an amplifying circuit formed on said semiconductor substrate; and

a detecting step for detecting an amplification output obtained in said amplifying step.

12. A semiconductor device characterized by comprising, on a semiconductor substrate:

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines;

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing; and

amplifying means for amplifying a potential level occurring in said data line for output to an external testing device.

13. A semiconductor device as claimed in claim 12, characterized in that:

a selecting circuit for alternatively selecting a data line to be connected to said amplifying means from a plurality of said data lines is formed on said semiconductor substrate.

14. A display apparatus characterized by comprising:

a semiconductor substrate;

a counter substrate having a common electrode and disposed opposite to the semiconductor substrate; and

a liquid crystal layer interposed between said semiconductor substrate and said counter substrate;

wherein said semiconductor substrate includes;

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines;

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing; and

amplifying means for receiving a potential level occurring in said data line and amplifying the received potential level for output to an external testing device.

15. A display apparatus as claimed in claim 14, characterized in that:

a selecting circuit for alternatively selecting a data line to be connected to said amplifying means from a plurality of said data lines is formed on said semiconductor substrate.

16. A testing method for testing a semiconductor substrate, said semiconductor substrate being formed with pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data, said method characterized by comprising:

a charge retaining step for making pixel capacitances connected to a plurality of pixel switches selected from all pixel switches connected to one data line retain charge;

a potential generating step for generating, in said one data line, a potential level corresponding to the charge retained in a plurality of the pixel capacitances in said charge retaining step;

an amplifying step for amplifying the potential level generated in said data line in said potential generating step by an amplifying circuit formed on said semiconductor substrate; and

a detecting step for detecting an amplification output obtained in said amplifying step.

17. A semiconductor device characterized by comprising, on a semiconductor substrate:

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines, and for testing, generating a testing scanning signal for simultaneously turning on an arbitrary plurality of pixel switches on one of said data lines;

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing; and

amplifying means for amplifying a potential level occurring in said data line for output to an external testing device.

18. A display apparatus characterized by comprising:

a semiconductor substrate;

a counter substrate having a common electrode and disposed opposite to the semiconductor substrate; and

a liquid crystal layer interposed between said semiconductor substrate and said counter substrate;

wherein said semiconductor substrate includes;

pixel cell driving circuits arranged in a form of a matrix in correspondence with positions of intersection of data lines and pixel switch control lines, said pixel cell driving circuits each including a pixel switch and a pixel capacitance connected to the pixel switch, for retaining pixel data;

vertical scanning means for scanning in a vertical direction by sequentially outputting a scanning signal for turning on said pixel switch to said pixel switch control lines, and for testing, generating a testing scanning signal for simultaneously turning on an arbitrary plurality of pixel switches;

horizontal scanning means for scanning in a horizontal direction by applying a data signal to said data lines in predetermined timing; and

amplifying means for amplifying a potential level occurring in said data line for output to an external testing device.

19. A display apparatus as claimed in claim 18, characterized in that:

a selecting circuit for alternatively selecting a data line to be connected to said amplifying means from a plurality of said data lines is formed on said semiconductor substrate.