Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
First Claim
1. A refresh controller for use in a dynamic random access memory (“
- DRAM”
) having a full density mode and a reduced density mode, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal;
a first selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and to apply the second periodic clock signal to the output terminal in the reduced density mode;
a counter having a clock input terminal coupled to the output terminal of the first selector circuit, the counter having first and second stages the first of which increments at a faster rate than the second; and
a second selector circuit coupled the first and second stages of the counter, the second selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode.
1 Assignment
0 Petitions
Accused Products
Abstract
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.
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Citations
47 Claims
-
1. A refresh controller for use in a dynamic random access memory (“
- DRAM”
) having a full density mode and a reduced density mode, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal;
a first selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and to apply the second periodic clock signal to the output terminal in the reduced density mode;
a counter having a clock input terminal coupled to the output terminal of the first selector circuit, the counter having first and second stages the first of which increments at a faster rate than the second; and
a second selector circuit coupled the first and second stages of the counter, the second selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode. - View Dependent Claims (2, 3, 4, 5, 6)
- DRAM”
-
7. A refresh controller for use in a dynamic random access memory (“
- DRAM”
) having a full density mode and a reduced density mode, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal; and
a selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and lo apply the second periodic clock signal to the output terminal in the reduced density mode. - View Dependent Claims (8, 9, 10)
- DRAM”
-
11. A refresh controller for use in a dynamic random access memory (“
- DRAM”
) having a full density mode and a reduced density mode, the refresh controller comprising;
an oscillator generating a periodic clock signal;
a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second; and
a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode. - View Dependent Claims (12, 13, 14, 26)
- DRAM”
-
15. A refresh controller for use in a dynamic random access memory (“
- DRAM”
) having a full density mode and a reduced density mode, the refresh controller comprising;
a toggle circuit receiving an auto refresh command and being structured to generate an enable signal responsive to only a portion of a plurality of auto-refresh commands;
a gate having a first input coupled to the toggle circuit and a second input receiving each of the plurality of auto-refresh commands, the gate being structured to generate a refresh signal responsive to each auto-refresh command when the gate is enabled by the enable signal from the toggle circuit. - View Dependent Claims (16)
- DRAM”
-
17. A circuit for remapping a specific row address bit to a specific column address bit, comprising:
-
a first latch coupled to receive the specific row address bit, the latch being operable to store the specific row address bit responsive to a row address strobe signal and to then output the stored row address bit;
a second latch coupled to receive a first set of column address bits and the specific column address bit, the latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and
a selector operable to select either the specific row address bit output from the first latch or the specific column address bit output from the second latch, the selected address bit being combined with the column address bits in the first set. - View Dependent Claims (18)
-
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19. A dynamic random access memory (“
- DRAM”
) comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal;
a first selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in a full density mode and to apply the second periodic clock signal to the output terminal in a reduced density mode;
a counter having a clock input terminal coupled to the output terminal of the first selector circuit, the counter having first and second stages the first of which increments at a faster rate than the second; and
a second selector circuit coupled the first and second stages of the counter, the second selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the counter stage coupled to the output terminal by the second selector circuit being incremented or decremented. - View Dependent Claims (20, 21, 22, 23)
- DRAM”
-
24. A dynamic random access memory (“
- DRAM”
) comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in a full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal; and
a selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and to apply the second periodic clock signal to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the periodic clock signal being coupled to the output terminal. - View Dependent Claims (25)
- DRAM”
-
27. A dynamic random access memory (“
- DRAM”
) comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in a full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
an oscillator generating a periodic clock signal;
a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second; and
a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the counter stage coupled to the output terminal by the selector circuit being incremented or decremented. - View Dependent Claims (28, 29)
- DRAM”
-
30. A dynamic random access memory (“
- DRAM”
) comprising;
an array of memory cells arranged in rows and columns;
a circuit for remapping a specific row address bit to a specific column address bit, comprising;
a remapping latch coupled to receive the specific row address bit, the remapping latch being operable to store the specific row address bit responsive to a row address strobe signal and to then output the stored row address bit;
a column address latch coupled to receive a first set of column address bits and the specific column address bit, the column address latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and
a selector operable to select either the specific row address bit output from the remapping latch in a reduced density mode or the specific column address bit output from the column address latch in a full density mode, the selected address bit being combined with the column address bits in the first set to provide a composite column address;
a column decoder coupled to the selector to receive the composite column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in the reduced density mode regardless of the state of the least significant bit of the row address; and
a data path coupled between the memory array and a data terminal. - View Dependent Claims (31)
- DRAM”
-
32. A dynamic random access memory (“
- DRAM”
) comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the fall density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
a toggle circuit receiving an auto refresh command and being structured to generate an enable signal responsive to only a portion of a plurality of auto-refresh commands;
a gate having a first input coupled to the toggle circuit and a second input receiving each of the plurality of auto-refresh commands, the gate being structured to generate a refresh signal responsive to each auto-refresh command when the gate is enabled by the enable signal from the toggle circuit.
- DRAM”
-
33. A computer system, comprising:
-
a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a dynamic random access memory, comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in a full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
an oscillator generating a first periodic clock signal;
a frequency division circuit coupled to receive the periodic clock signal, the frequency division circuit being operable to generate a second periodic clock signal having a frequency that is less than the frequency of the first periodic signal; and
a selector circuit coupled to receive the first periodic clock signal from the oscillator and the second periodic clock signal from the frequency division circuit, the first selector circuit being operable to apply the first periodic clock signal to an output terminal in the full density mode and to apply the second periodic clock signal to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the periodic clock signal being coupled to the output terminal. - View Dependent Claims (34, 35)
-
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36. A computer system, comprising:
-
a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a dynamic random access memory, comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
an oscillator generating a periodic clock signal;
a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second; and
a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the counter stage coupled to the output terminal by the selector circuit being incremented or decremented. - View Dependent Claims (37, 38)
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39. A computer system, comprising:
-
a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a dynamic random access memory, comprising;
an array of memory cells arranged in rows and columns;
a circuit for remapping a specific row address bit to a specific column address bit, comprising;
a remapping latch coupled to receive the specific row address bit, the remapping latch being operable to store the specific row address bit responsive to a row address strobe signal and to then output the stored row address bit;
a column address latch coupled to receive a first set of column address bits and the specific column address bit, the column address latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and
a selector operable to select either the specific row address bit output from the remapping latch in a reduced density mode or the specific column address bit output from the column address latch in a full density mode, the selected address bit being combined with the column address bits in the first set to provide a composite column address;
a column decoder coupled to the selector to receive the composite column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in the reduced density mode regardless of the state of the least significant bit of the row address; and
a data path coupled between the memory array and a data terminal. - View Dependent Claims (40)
-
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41. A computer system, comprising:
-
a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a dynamic random access memory, comprising;
an array of memory cells arranged in rows and columns;
a column address latch structured to store a column address responsive to a column address strobe signal;
a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;
a row address latch structured to store a row address responsive to a row address strobe signal;
a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;
a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;
a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;
a data path coupled between the memory array and a data terminal; and
a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;
a toggle circuit receiving an auto refresh command and being structured to generate an enable signal responsive to only a portion of a plurality of auto-refresh commands;
a gate having a first input coupled to the toggle circuit and a second input receiving each of the plurality of auto-refresh commands, the gate being structured to generate a refresh signal responsive to each auto-refresh command when the gate is enabled by the enable signal from the toggle circuit.
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42. A method of refreshing a dynamic random access memory (“
- DRAM”
) having a full density operating mode and a reduced density operating mode, the method comprising;
determining the operating mode of the DRAM;
if the DRAM is determined to be operating in the full density mode, refreshing the DRAM at a first rate; and
if the DRAM is determined to be operating in the reduced density mode, refreshing the DRAM at a second rate, the second rate being slower than the first rate. - View Dependent Claims (43)
- DRAM”
-
44. A method of addressing a dynamic random access memory (“
- DRAM”
) having a full density operating mode and a reduced density operating mode, the method comprising;
determining the operating mode of the DRAM;
storing a specific row address bit responsive to a row address strobe signal;
storing a first set of column address bits and a specific column address bit responsive to a column address strobe signal; and
in the full density operating mode, selecting the first set of column address bits and the specific column address bit that were stored responsive to the column address strobe signal;
in the reduced density operating mode, selecting the first set of column address bits that were stored responsive to the column address strobe signal and the specific row address bit that was stored responsive to the row address strobe signal; and
addressing a column of the the DRAM using the selected address bits. - View Dependent Claims (45)
- DRAM”
-
46. A method of refreshing a dynamic random access memory (“
- DRAM”
) having a full density operating mode and a reduced density operating mode, the method comprising;
applying a plurality of auto-refresh commands to the DRAM;
determining the operating mode of the DRAM;
if the DRAM is determined to be operating in the full density mode, refreshing the DRAM responsive to each of the plurality of auto-refresh commands; and
if the DRAM is determined to be operating in the reduced density mode, refreshing the DRAM responsive to less than each of the plurality of auto-refresh commands. - View Dependent Claims (47)
- DRAM”
Specification