Communication system and method for generating slave clocks and sample clocks at the source and destination ports of a synchronous network using the network frame rate

• US 20040032883A1
• Filed: 08/14/2002
• Published: 02/19/2004
• Est. Priority Date: 08/14/2002
• Status: Active Grant

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Knapp, David J., Winkelmann, Matthias, Akkihal, Shivanand I.
• Granted Patent: US 7,272,202 B2
• Time in Patent Office: Days
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0647 Synchronisation among TDM nodes
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. The sample rate converter simply produces a play rate from the transmitted information at the destination. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode. As a further alternative, sample rates within the source and destination ports can be derived from the network frame rate using fractional dividers in the source and destination ports.

Claims

1. A source port of a communication network, comprising a circuit that receives a frame transfer rate of the network and produces a master clock from which subsystems of the source port are synchronized, and wherein the master clock has a frequency of an integer multiple of approximately 1125/2 of the frame transfer rate of 48 KHz or an integer multiple of approximately 30000/49 of the frame transfer rate of 44.1 KHz.

2. The source port as recited in claim 1, wherein the master clock transitions at a frequency of 27 MHz.

3. The source port as recited in claim 1 is embodied upon a single monolithic substrate.

4. The source port as recited in claim 1, wherein the transfer clock transitions at a frequency synchronous with a rate at which a plurality of frames are sent across the network.

5. The source port as recited in claim 1, further comprising a multimedia device adapted to produce audio data at a rate of M/N times the master clock.

6. The source port as recited in claim 5, wherein the audio data rate is 48 KHz or 44.1 KHz.

7. The source port as recited in claim 1, wherein the circuit comprises a phase-locked loop.

8. A destination port of a communication network, comprising a circuit coupled to receive a frame transfer rate of the network and produce a sample clock from which subsystems of the destination node are synchronized, and wherein the sample clock has a frequency of integer multiples of approximately 147/160 or 160/147 of the frame transfer rate.

9. The destination port as recited in claim 8 is embodied upon a single monolithic substrate.

10. The destination port as recited in claim 8, wherein the frame transfer rate transitions at a frequency synchronous with a rate at which a plurality of frames are sent across the network.

11. The destination port as recited in claim 8, wherein the frame transfer rate is approximately 48 KHz and the sample clock transitions at a frequency of 48 KHz×

147/160.

12. The destination port as recited in claim 8, wherein the frame transfer rate is approximately 44.1 KHz and the sample clock transitions at a frequency of 44.1 KHz×

160/147.

13. The destination port as recited in claim 8, wherein the circuit comprise a phase-locked loop.

14. A communication network, comprising:

a source port;

a destination port coupled to the source port by the network;

a plurality of frames of data, each of which are transferred across the network at a frame transfer rate; and

a circuit configured within the source port and the destination port to produce a source sample rate and a destination sample rate of substantially equal frequency by dividing and multiplying the frame transfer rate.

15. The communication network as recited in claim 14, wherein the network is a synchronous network.

16. The communication network as recited in claim 14, wherein a portion of the circuit within the source port is adapted to multiply and divide the frame transfer rate to produce a master clock from which subsystems of the source port are synchronized, and wherein the master clock has a frequency of approximately 1125/2 of the frame transfer rate of 48 KHz or 30000/49 of the frame transfer rate of 44.1 KHz.

17. The communication network as recited in claim 16, wherein the portion of the circuit produces the master clock from the frame transfer rate and another portion of the circuit produces the source sample rate from the master clock.

18. The communication network as recited in claim 14, wherein a portion of the circuit within the destination port is adapted to multiply and divide a frame transfer rate of the network to produce the destination sample rate from which subsystems of the destination port are synchronized, and wherein the destination sample rate has a frequency of approximately 147/160 or 160/147 of the frame transfer rate.

19. The communication network as recited in claim 14, wherein the frame transfer rate is approximately 48 KHz and the destination sample rate transitions at a frequency of 48 KHz×

147/160.

20. The communication network as recited in claim 14, wherein the frame transfer rate is approximately 44.1 KHz and the destination sample rate transitions at a frequency of 44.1 KHz×

160/147.

21. The communication network as recited in claim 14, wherein the circuit comprises a phase-locked loop.

22. A method for generating a sampling clock local to a node of a communication network, comprising:

converting a frame transfer rate of a network according to a first fractional amount at a source port to produce a sampling clock at the source port; and

converting the frame transfer rate of the network according to a second fractional amount equal to the first fractional amount at a destination port to produce a sampling clock at the destination port.

23. The method as recited in claim 22, wherein the first fractional amount comprises a combination of a first sub-fractional amount and a second sub-fractional amount, wherein the first sub-fractional amount converts the frame transfer rate to a rate of a master clock and the second sub-fractional amount converts the master clock transfer rate to the sampling clock at the source port.

24. The method as recited in claim 22, wherein the first sub-fractional amount is equal to 1125/2 or 30000/49.