Arrangement for dynamic DC offset compensation

• US 20040032914A1
• Filed: 08/19/2002
• Published: 02/19/2004
• Est. Priority Date: 08/19/2002
• Status: Active Grant

• Current Assignee: Siemens AG
• Original Assignee: Siemens Communications Incorporated (Siemens AG)
• Inventors: Klingenbrunn, Thomas, Rouphael, Antoine J., Vejlgaard, Benny, Chu, Lichung
• Granted Patent: US 7,190,740 B2
• Time in Patent Office: Days
• US Class Current: 375/313
• CPC Class Codes: H04L 25/03305 Joint sequence estimation and interference removal joint detection of several desired signals H04L25/03331
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178

Abstract

A DC tracking arrangement comprises a first tracking unit for slow tracking receiving an input signal and generating a first output signal, a second tracking unit for fast tracking receiving the input signal and generating a second output signal, and a decision unit receiving the first and second output signal for selecting the first or second output signal.

Claims

1. A DC tracking arrangement comprising:

a first tracking unit for slow tracking receiving an input signal and generating a first output signal;

a second tracking unit for fast tracking receiving the input signal and generating a second output signal; and

a decision unit receiving the first and second output signal for selecting the first or second output signal.

2. The arrangement as in claim 1, wherein the first tracking unit is a narrow band filter and the second tracking unit is a wide band filter.

3. The arrangement as in claim 1, wherein the decision unit compares the absolute difference of the first and second filter output with a predefined threshold.

4. The arrangement as in claim 3, wherein each filter comprises a feedback input receiving a feedback signal from said decision unit.

5. The arrangement as in claim 3, wherein the threshold is the root-mean-square of the input signal times a constant.

6. The arrangement according to claim 1, further comprising an upper bounding unit for limiting the input signal.

7. The arrangement according to claim 6, wherein the upper bounding unit resets the input signal if the input signal is greater than a predetermined value.

8. The arrangement according to claim 1, further comprising a rotation unit for rotating the input signal wherein the rotation unit receives the input signal and is coupled with the first and second filter and a de-rotation unit coupled to the output of the decision unit.

9. A Viterbi equalizer comprising a plurality of states, wherein each state comprises a DC tracking arrangement comprising:

a first tracking unit for slow tracking receiving an input signal and generating a first output signal;

a second tracking unit for fast tracking receiving the input signal and generating a second output signal; and

a decision unit receiving the first and second output signal for selecting the first or second output signal.

10. The Viterbi equalizer as in claim 9, wherein the first tracking unit is a narrow band filter and the second tracking unit is a wide band filter.

11. The Viterbi equalizer as in claim 9, wherein the decision unit compares the absolute difference of the first and second filter output with a predefined threshold.

12. The Viterbi equalizer as in claim 11, wherein each filter comprises a feedback input receiving a feedback signal from said decision unit.

13. The Viterbi equalizer as in claim 10, wherein the threshold is the root-mean-square of the input signal times a constant.

14. The Viterbi equalizer as in claim 9, further comprising an upper bounding unit for limiting the input signal.

15. The Viterbi equalizer as in claim 14, wherein the upper bounding unit resets the input signal if the input signal is greater than a predetermined value.

16. The Viterbi equalizer as in claim 9, further comprising a rotation unit for rotating the input signal wherein the rotation unit receives the input signal and is coupled with the first and second filter and a de-rotation unit coupled to the output of the decision unit.

17. The Viterbi equalizer as in claim 9, wherein each state receives a plurality of DC offset values and a input symbol further comprising:

a plurality of subtractors for subtracting one of the plurality of DC offset values from the input symbol and generating an output signal;

a plurality of metric calculation units each receiving a respective output signal from an associated subtractor for providing a metric output signal;

a compare unit receiving the plurality of metric output signals for generating an error signal which is used as the input signal for the DC tracking arrangement.

18. A method of determining and tracking a DC offset in a digital signal stream used for symbol detection comprising the steps of:

providing a digital signal stream to an equalizer for symbol determination;

determining an error value for each symbol;

narrow band filtering the error value for slow tracking of the DC offset;

wide band filtering the error value for fast tracking of the DC offset;

comparing the output values of the narrow and wide band filtering and selecting the narrow or wide band output values as a DC offset value.

19. The method as in claim 18, wherein the narrow band filtering is a low pass filtering and the wide band filtering is a high pass filtering.

20. The method as in claim 18, wherein the step of comparing comprises:

comparing the absolute difference of the output values of the narrow band and the wide band filtering with a predefined threshold.

21. The method as in claim 20, wherein the threshold is based upon the root-mean-square value of the digital signal stream.

22. The method as in claim 18, further comprising the step of upper-bounding the input signal.

23. The method as in claim 22, wherein the step of upper-bounding includes the step of comparing the input signal with a predetermined value and resetting the input signal if the input signal is greater than the predetermined value.

24. The method as in claim 18, further comprising the step of rotating the input signal before determination of the DC offset and de-rotating the signal after determination of the DC offset.