Electronic components and method of fabricating the same

• US 20040033676A1
• Filed: 04/23/2003
• Published: 02/19/2004
• Est. Priority Date: 04/23/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Coronel, Philippe, Skotnicki, Thomas, Leverd, Francois
• Granted Patent: US 7,214,597 B2
• Time in Patent Office: Days
• US Class Current: 438/484
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H10B 12/033 : the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0387 : Making the trench
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10K 71/18 : using non-liquid printing techniques, e.g. thermal transfer printing from a donor sheet

Abstract

A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Claims

1. A method of fabricating integrated electronic components, said method comprising the steps of:

producing an initial structure on the surface of a first substrate, the initial structure including a plurality of volumes of materials, some of these volumes forming a defined pattern;

transferring at least a part of the initial structure that includes the defined pattern from the first substrate onto a second substrate; and

producing an additional structure on the second substrate using at least some of the volumes of materials of the defined pattern as self-alignment marks of the additional structure with respect to the part of the initial structure that was transferred.

2. The method of claim 1, wherein the transferring step includes the sub-steps of:

inverting the first substrate;

applying the first substrate against the second substrate via the initial structure; and

removing the first substrate.

3. The method of claim 1, wherein the initial structure includes at least two stacked levels of volumes of material on the surface of the first substrate.

4. The method of claim 3, wherein the initial structure includes at least two volumes of material that cover at least some of the volumes of material forming the defined pattern.

5. The method of claim 1, wherein the step of producing an initial structure includes the sub-step of carrying out a treatment for differentiating at least one of the volumes of material forming the defined pattern from the other volumes of material forming the defined pattern.

6. The method of claim 5, wherein the treatment is at least one of:

deposition of a defined material in the volume, implantation of chemical species in an initial material of the volume, and a chemical reaction generated in at least part of an initial material of the volume.

7. The method of claim 1, wherein the material of at least one of the volumes of the defined pattern is silicon-based.

8. The method of claim 1, wherein the material of at least one of the volumes of the defined pattern is silicon nitride-based.

9. The method of claim 1, further including the step of:

between the transferring step and the step of producing an additional structure, providing an access to at least part of the volumes of the pattern.

10. The method of claim 9, further including the step of carrying out a selective treatment through the access, in order to distinguish at least one of the volumes of material forming the defined pattern from the other volumes of material forming the defined pattern.

11. The method of claim 10, wherein the selective treatment is at least one of:

etching using a solution including chemical reactants, etching using a plasma, and deposition of a material.

12. The method of claim 10,

wherein the material of at least one of the volumes of the pattern is crystalline, and

the selective treatment includes deposition of a material by epitaxial growth from at least one surface of the crystalline material.

13. The method of claim 2, wherein the initial structure includes at least one upper volume via which the first substrate supporting the initial structure is applied against the second substrate, the material of the upper volume being suitable for adhering to the surface portion of the second substrate.

14. The method of claim 13, wherein the material suitable for adhering to the surface portion of the second substrate is based on a material chosen from:

silicon, silica, a silicon-based material, and a silica-based material.

15. The method of claim 1, further comprising the step of:

after the transferring step, covering the second substrate with a material chosen from;

silicon, silica, a silicon-based material, and a silica-based material.

16. An integrated electronic component fabricated by a method comprising the steps of:

producing an initial structure on the surface of a first substrate, the initial structure including a plurality of volumes of materials, some of these volumes forming a defined pattern;

transferring at least a part of the initial structure that includes the defined pattern from the first substrate onto a second substrate; and

producing an additional structure on the second substrate using at least some of the volumes of materials of the defined pattern as self-alignment marks of the additional structure with respect to the part of the initial structure that was transferred.

17. The integrated electronic component according to claim 16, wherein the integrated electronic component comprises a transistor.

18. The integrated electronic component according to claim 16, wherein the integrated electronic component comprises a diode.

19. The integrated electronic component according to claim 16, wherein the integrated electronic component comprises at least a portion of a dynamic random access memory element.

20. An integrated circuit including at least one integrated electronic component that is fabricated by a method comprising the steps of:

producing an initial structure on the surface of a first substrate, the initial structure including a plurality of volumes of materials, some of these volumes forming a defined pattern;

transferring at least a part of the initial structure that includes the defined pattern from the first substrate onto a second substrate; and

producing an additional structure on the second substrate using at least some of the volumes of materials of the defined pattern as self-alignment marks of the additional structure with respect to the part of the initial structure that was transferred.