Method and apparatus for measuring fault diagnostics on insulated gate bipolar transistor converter circuits

• US 20040034508A1
• Filed: 05/28/2003
• Published: 02/19/2004
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Siemens VDO Automotive Corporation (Siemens AG)
• Original Assignee: Ballard Power Systems Corporation (Superior Plus Corporation)
• Inventors: Harmon, Kent M., Cheng, Bing
• Granted Patent: US 6,927,988 B2
• Time in Patent Office: Days
• US Class Current: 702/185
• CPC Class Codes: B60L 3/003 relating to inverters
• CPC Class Codes: G01R 31/42 AC power supplies
• CPC Class Codes: H02P 27/06 using dc to ac converters or inverters H02P27/05 takes precedence
• CPC Class Codes: H02P 29/02 Providing protection against overload without automatic interruption of supply protection against faults of stepper motors H02P8/36
• CPC Class Codes: Y02T 10/64 Electric machine technologies in electromobility

Abstract

A method for diagnosing faults using a load. In the method IGBTs are controlled such that certain currents are expected. If the currents are not as expected, a fault may be diagnosed.

Claims

1. A fault determination method for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

selectively placing in a conducting state at least one of the upper IGBTs during a first time and selectively placing in a conducting state at least one of the lower IGBTs during the first time; and

determining a set of IGBT operational states in response to at least one of a magnitude and a direction of a current through a load between the at least one upper and the at least one lower IGBT placed in the conducting state during the first time.

2. The method of claim 1 wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and further wherein the selectively placing in a conducting state at least one of the upper IGBTs during a first time and selectively placing in a conducting state at least one of the lower IGBTs during the first time further comprises:

turning on the first and the second upper IGBT during the first time and turning on the third lower IGBT during the first time.

3. The method of claim 1 wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and further wherein the selectively placing in a conducting state at least one of the upper IGBTs during a first time and selectively placing in a conducting state at least one of the lower IGBTs during the first time further comprises:

turning on the first and the second lower IGBT during the first time and turning on the third upper IGBT during the first time.

4. The method of claim 1 wherein the selectively placing in a conducting state at least one of the upper IGBTs during a first time and selectively placing in a conducting state at least one of the lower IGBTs during the first time further comprises:

turning on an upper IGBT during the first time and turning on a lower IGBT during the first time.

5. The method of claim 1 wherein the determining a set of IGBT operational states in response to at least one of a magnitude and a direction of a current through a load between the at least one upper and the at least one lower IGBT placed in the conducting state during the first time further comprises:

concluding that the set includes at least one of the following

(a) an operational state wherein all IGBTs in the power converter are normal,

(b) an operational state wherein at least one IGBT in one phase is faulty,

(c) an operational state wherein at least one IGBT in two phases is faulty, and

(d) an operational state wherein at least one IGBT in three phases is faulty.

6. The method of claim 1 further comprising:

selectively placing in a conducting state at least one of the lower IGBTs or at least one of the upper IGBTs during a second time; and

selecting one operational state from the set of IGBT operational states in response to at least one of a magnitude and a direction of at least one current through the least one of the lower IGBTs or the at least one of the upper IGBTs placed in the conducting state during the second time.

7. The method of claim 1 wherein the selecting is further in response to at least one measured collector-emitter voltage indicative of a fault current.

8. A fault determination system for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

means for selectively placing in a conducting state at least one of the upper IGBTs during a first time and selectively placing in a conducting state at least one of the lower IGBTs during the first time; and

means for determining a set of IGBT operational states in response to at least one of a magnitude and a direction of a current through a load between the at least one upper and the at least one lower IGBT placed in the conducting state during the first time.

9. A fault determination method for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

during a first time interval,

controlling at least one of the upper IGBTs and at least one of the lower IGBTs such that during at least one first-time-interval expected current will flow through a part of a resistive network if the at least one upper IGBT and the at least one lower IGBT are normal,

sensing at least one of a magnitude and a direction of at least one first-time-interval current through the part of the resistive network,

comparing the at least one first-time-interval sensed current with the at least one first-time-interval expected current, and

determining a state of at least one IGBT in response to the comparing.

10. The method of claim 9, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first upper IGBT, the second upper IGBT, and the third lower IGBT such that if the first upper, the second upper and the third lower IGBT are normal,

a first expected current will flow through a first resistor in series with the first upper IGBT and a node,

a second expected current will flow through a second resistor in series with the second upper IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in at least one of the first and the second resistors with a predetermined current value, and

concluding that the first upper IGBT, the second upper IGBT, and the third lower IGBT are normal in response to the comparing showing that the current in the first and the second resistors is balanced and within tolerance of a predetermined current value.

11. The method of claim 9, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first lower IGBT, the second lower IGBT, and the third upper IGBT such that if the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal,

a first expected current will flow through a first resistor in series with the first lower IGBT and a node,

a second expected current will flow through a second resistor in series with the second lower IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third upper IGBT, and

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in at least one of the first and the second resistors with a predetermined current value, and

concluding that the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal in response to the comparison determining that the current in the first and the second resistors is balanced and within tolerance of a negative predetermined current value.

12. The method of claim 9, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first upper IGBT, the second upper IGBT, and the third lower IGBT such that if the first upper, the second upper, and the third lower IGBT are normal,

a first expected current will flow through a first resistor in series with the first upper IGBT and a node,

a second expected current will flow through a second resistor in series with the second upper IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors, and

concluding that either the first upper IGBT is potentially open or a first lower IGBT is potentially shorted if the magnitude of the current in at least one of the first and the second resistors is substantially zero.

17. The method of claim 9, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first lower IGBT, the second lower IGBT, and the third upper IGBT such that if the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal,

a first expected current will flow through a first resistor in series with the first lower IGBT and a node,

a second expected current will flow through a second resistor in series with the second lower IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

determining if the magnitude of the current in at least one of the first and the second resistors is substantially zero, and

concluding that either the third upper IGBT is open or that the third lower IGBT shorted in response to a determination that the magnitude of the current in at least one of the first and the second resistors is substantially zero and that a DESAT signal of at least one upper IGBT is active.

18. The method of claim 17, further comprising:

during a second time interval,

turning ON the first upper IGBT, the second upper IGBT, and the third lower IGBT such that if the first upper IGBT, the second upper IGBT, and the third lower IGBT are normal,

a first expected current will flow through a first resistor in series with the first upper IGBT and a node,

a second expected current will flow through a second resistor in series with the second upper IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the at least one of the first and the second resistors with the predetermined current value, and

concluding that the first lower IGBT, the second lower IGBT, are normal, and that the third lower IGBT is potentially shorted in response to the comparison determining that currents in the first and the second resistors are balanced and within tolerance of a negative of a predetermined current value.

19. The method of claim 18, further comprising:

during a third time interval,

turning ON the first upper IGBT and the second lower IGBT such that current will flow through the first upper IGBT and the second lower IGBT and bypass the third resistor if the first upper IGBT and the second lower IGBT are normal and no other IGBTs are shorted,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with the predetermined current value, and

concluding that the third upper IGBT is open in response to the comparison determining that the magnitude and the direction of the current in the first resistor is a positive multiple of the predetermined current value and concluding that the third lower IGBT is shorted in response to the comparison determining that the magnitude and the direction of the current in the first resistor is a negative of the predetermined current value.

20. The method of claim 19, further comprising:

during a fourth time interval,

turning ON the first lower IGBT and the second upper IGBT such that current will flow through the first lower IGBT and the second upper IGBT and bypass the third resistor if the first lower IGBT and the second upper IGBT are normal and no other IGBTs are shorted,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with the predetermined current value, and

concluding that the third lower IGBT is shorted, and that the first lower IGBT and the second upper IGBT are normal in response to the comparison determining that the magnitude and the direction of the current in the second resistor equals the predetermined current value and concluding that the third upper IGBT is open, and that the first lower IGBT and the second upper IGBT are normal in response to the comparison determining that the magnitude and the direction of the current in the second resistor is a positive multiple of the predetermined current value.

21. The method of claim 9, wherein the power converter circuit has a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first upper IGBT, the second upper IGBT, and a third lower IGBT such that if the first upper IGBT, the second upper IGBT, and the third lower IGBT are normal,

a first expected current will flow through a first resistor (R1) in series with the first upper IGBT and a node,

a second expected current will flow through a second resistor (R2) in series with the second upper IGBT and the node, and

a third current will flow through a third resistor (R3) in series with the node and the THIRD IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors, and

concluding the first upper IGBT is open or the first lower IGBT is potentially shorted or the second upper IGBT is open or the second IGBT is potentially shorted in response to a determination that the magnitude and the direction of the current in at least one of the first and the second resistors is substantially zero and that a DESAT signal of at least one upper IGBT is active.

22. The method of claim 21, further comprising;

during a second time interval,

turning ON the first lower IGBT, the second lower IGBT, and the third upper IGBT such that if the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal,

a first expected current will flow through a first resistor in series with the first lower IGBT and a node,

a second expected current will flow through a second resistor in series with the second lower IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with a predetermined current value, and

concluding that at least one of the first and the second lower IGBTs are shorted in response to the comparison determining that the current in at least one of the first resistor and the current in the second resistor are a negative of the predetermined current value.

23. The method of claim 22, further comprising:

during a third time interval,

turning ON the third upper IGBT such that no current will flow if no other IGBTs are shorted,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with a predetermined current value,

concluding that the first and the second lower IGBTs are shorted in response to the comparison determining that the current in the first resistor and the second resistor are balanced and equal a negative of the predetermined current value,

concluding that the first lower IGBT is shorted and the second lower IGBT is potentially open in response to the comparison determining that the current in the first resistor is a negative multiple of the predetermined current value and the current in the second resistor is substantially zero,

concluding that the first lower IGBT is potentially open and the second lower IGBT is shorted in response to the comparison determining that the current in the second resistor is a negative multiple of the predetermined current value and the current in the first resistor is substantially zero, and

concluding that the first lower IGBT is normal and the second lower IGBT is normal in response to the comparison determining that the magnitude of the currents in the first and the second resistors is substantially zero.

24. The method of claim 9, wherein the power converter circuit has a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval,

turning ON the first upper IGBT, the second upper IGBT, and the third lower IGBT such that if the first upper IGBT, the second upper IGBT, and the third lower IGBT are normal,

a first expected current will flow through a first resistor in series with the first upper IGBT and a node,

a second expected current will flow through a second resistor in series with the second upper IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third lower IGBT,

sensing at least one of a magnitude and a direction of a current in the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with a predetermined current value,

concluding that a potential short exists in the first lower IGBT or the third lower IGBT if the magnitude of the current in at least one of the first and the second resistors is substantially zero and a DESAT signal of at least one of the IGBTs is active.

25. The method of claim 24, further comprising;

during a second time interval,

turning ON the first lower IGBT, the second lower IGBT, and the third upper IGBT such that if the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal,

a first expected current will flow through a first resistor in series with the first lower IGBT and a node,

a second expected current will flow through a second resistor in series with the second lower IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with a predetermined current value, and

concluding that a potential short exists in the first lower IGBT, the second lower IGBT, or the third lower IGBT if the magnitude of the current in at least one of the first and the second resistors is substantially zero.

26. The method of claim 25, further comprising:

during a third time interval,

turning ON the second upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in the first and the second resistors with a predetermined current value,

concluding that the first lower IGBT and the third lower IGBT are shorted in response to the comparison determining that the current in the first resistor is a negative of the predetermined current value and the current in the second resistor is a positive multiple of the predetermined current value,

concluding that the first lower IGBT is shorted in response to the comparison determining that the current in the first resistor is a negative multiple of the predetermined current value, and

concluding that the third lower IGBT is shorted in response to the comparison determining that the current in the second resistor is a negative multiple of the predetermined current value and the current in the first resistor is substantially zero.

13. The method 12, further comprising:

during a second time interval,

turning ON the first lower IGBT, the second lower IGBT, and the third upper IGBT such that if the first lower IGBT, the second lower IGBT, and the third upper IGBT are normal,

a first expected current will flow through a first resistor in series with the first lower IGBT and a node,

a second expected current will flow through a second resistor in series with the second lower IGBT and the node, and

a third current will flow through a third resistor in series with the node and the third upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second resistors,

comparing the at least one of the magnitude and the direction of the current in at least one of the first and the second resistors with a predetermined current value, and

concluding either that the first lower IGBT, second lower IGBT, and third upper IGBT are normal or that the first lower IGBT is potentially shorted in response to the comparison determining that currents in the first and the second resistors are balanced and within tolerance of a negative of a predetermined current value.

14. The method of claim 13, further comprising:

during a third time interval,

turning ON the third upper IGBT such that current will flow through the first resistor if the first lower IGBT is shorted, and

sensing at least one of a magnitude and a direction of a current in the first resistor, and

concluding that the first upper IGBT is open and that the first lower IGBT is not faulty if the magnitude of the current in the first resistor is substantially zero and concluding that the first lower IGBT is shorted if the current in the first resistor is a negative multiple of a predetermined current value.

15. The method of claim 14, further comprising:

during a fourth time interval,

turning ON the second upper IGBT and the third lower IGBT such that current will flow through the second and third resistors and bypass the first resistor if the second upper IGBT and the third lower IGBT are normal and no other IGBTs are shorted;

sensing at least one of a current magnitude and direction in the second resistor,

comparing the at least one of the magnitude and the direction of the current in the second resistor with the predetermined current value, and

concluding that the second upper IGBT and the third lower IGBT are normal in response to the comparison determining that the current in the second resistor is a negative multiple of a predetermined current value.

16. The method of claim 15, further comprising:

during a fifth time interval,

turning ON the second lower IGBT and the third upper IGBT such that current will flow through the second and third resistors and bypass the first resistor if the second lower IGBT and the third upper IGBT are normal and no other IGBTs are shorted,

sensing at least one of a current magnitude and direction in the second resistor,

comparing the at least one of the magnitude and the direction of the current in the second resistor with the predetermined current value, and

concluding that third upper IGBT and the second lower IGBT are normal in response to the comparison determining that the current in the second resistor is a positive multiple of a predetermined current value.

27. A fault determination system for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

means for, during a first time interval,

controlling at least one upper IGBT and at least one lower IGBT such that at least one first-time-interval expected current will flow through a part of a resistive network if the at least one upper IGBT and the at least one lower IGBT are normal,

sensing at least one of a magnitude and a direction of at least one first-time-interval current through the part of the resistive network, and

comparing the at least one first-time-interval sensed current with the at least one first-time-interval expected current, and

concluding a state of an IGBT in response to the comparing.

28. A fault determination method for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

during a first time interval and in response to a motor indicating a fault,

sequentially controlling at least one of the upper IGBTs and at least one of the lower IGBTs such that at least during one first-time-interval expected current will flow through a part of motor windings if the at least one upper IGBT and the at least one lower IGBT are normal, and

sensing at least one of a magnitude and a direction of at least one first-time-interval current through the part of the motor windings, and

concluding a state of at least one IGBT in response to the sensing.

29. The method of claim 28, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein the method further comprises:

during the first time interval and in response to the motor indicating a fault related to at least one of the first upper IGBT and the first lower IGBT,

turning ON the second upper IGBT such that if a short exists in the first lower IGBT a first current will flow through a first winding in series with a second winding, where the first winding is in series with the first upper and first lower IGBTs and the second winding is in series with both the second upper and second lower IGBTs,

sensing at least one of a magnitude and a direction of the first current in at least one of the first and the second windings, and

concluding that the first lower IGBT is shorted in response to the sensing showing that the first current in the first and the second windings has magnitude substantially equal to an input current.

30. The method of claim 29, further comprising:

during the first time interval,

turning OFF the second upper IGBT and thereafter turning ON the second lower IGBT such that if a short exists in a first lower IGBT a second current will flow through a first winding in series with a second winding, where the first winding is in series with the first upper and first lower IGBTs and the second winding is in series with both the second upper and second lower IGBTs,

sensing at least one of a magnitude and a direction of the second current in at least one of the first and the second windings, and

concluding that the first lower IGBT is shorted in response to the sensing showing that the second current in the first and the second windings has magnitude substantially equal to an input current.

31. The method of claim 30, further comprising:

during a second time interval,

sequentially turning ON the first upper IGBT and the second lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the first upper IGBT and the first lower IGBT are potentially normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

32. The method of claim 31, further comprising:

during a third time interval,

sequentially turning ON the first lower IGBT and the second upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the first upper IGBT and the first lower IGBT are potentially normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

33. The method of claim 28, wherein the N pairs of IGBTs comprises a first, a second, and a third upper IGBT respectively in series connection with a first, a second, and a third lower IGBT and wherein a first winding is in series with the first upper and the first lower IGBTs and a node, a second winding in series with the second upper and the second lower IGBTs and the node, and a third winding in series with the node and the third upper and the third lower IGBTs, and wherein the method further comprises:

during the first time interval and in response to the motor indicating a fault related to at least one of the first upper IGBT, the first lower IGBT, the third upper, and the third lower IGBT,

sequentially turning ON the second upper IGBT and the second lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the first lower IGBT is shorted in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to an input current,

concluding that the first lower IGBT and the third lower IGBT are shorted in response to determining that the sensed current in the second winding is twice the magnitude of the current in the first winding,

concluding that the third lower IGBT is shorted in response to determining that the sensed current in the second winding has a magnitude substantially equal to the input current and that the current in the first winding has substantially zero magnitude.

34. The method of claim 33, further comprising:

during a second time interval,

sequentially turning ON the first upper IGBT and the second lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the first upper IGBT and the first lower IGBT are potentially normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

35. The method of claim 34, further comprising:

during a third time interval,

sequentially turning ON the first lower IGBT and the second upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the first upper IGBT and the first lower IGBT are normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

36. The method of claim 35, further comprising:

during a fourth time interval,

sequentially turning ON the third upper IGBT and the second lower IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the third upper IGBT and the third lower IGBT are potentially normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

37. The method of claim 36, further comprising:

during a fifth time interval,

sequentially turning ON the third lower IGBT and the second upper IGBT,

sensing at least one of a magnitude and a direction of a current in at least one of the first and the second windings, and

concluding that the third upper IGBT and the third lower IGBT are normal in response to determining that the sensed currents in the first and the second windings are of equal magnitude and have magnitudes substantially equal to the input current.

38. A fault determination system for assessing a condition of a power converter circuit, the power converter circuit comprising a number N of pairs of insulated gate bipolar transistors (“

IGBTs”

), each pair of IGBTs comprising an upper IGBT coupled to a first polarity of a DC power source and a lower IGBT coupled to a second polarity of the DC power source, the method comprising;

means for, during a first time interval and in response to a motor indicating a fault,

sequentially controlling at least one upper IGBT and at least one lower IGBT such that at least one first-time-interval expected current will flow through a part of motor windings if the at least one upper IGBT and the at least one lower IGBT are normal, and

sensing at least one of a magnitude and a direction of at least one first-time-interval current through the part of the motor windings, and

comparing the at least one first-time-interval sensed current with the at least one first-time-interval expected current, and

concluding a state of at least one IGBT in response to the comparison.