Memory hub bypass circuit and method

• US 20040034753A1
• Filed: 08/16/2002
• Published: 02/19/2004
• Est. Priority Date: 08/16/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 7,149,874 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests for access to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface coupling memory requests to the memory devices and generating a status signal indicating whether or not at least one of the memory requests is being serviced;

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit generating and coupling a portion of each of the memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer generating and coupling memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is being serviced and generating and coupling the remaining portion of each of the memory requests not handled by the bypass circuit from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.

2. The memory module of claim 1 wherein the status signal comprises:

an active signal indicating that at least one of the memory requests is being serviced; and

an idle signal indicating that at least one of the memory requests is not being serviced.

3. The memory module of claim 1 wherein the memory hub further comprises a multiplexer having data inputs coupled to the sequencer and the bypass circuit, a data output coupled to the memory device interface and a control input coupled to receive the status signal from the memory device interface, the multiplexer coupling the memory requests from the sequencer responsive to the status signal indicating that at least one of the memory requests is being serviced and coupling a portion of the memory request from the bypass circuit and a portion from the sequencer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

4. The memory module of claim 1 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.

5. The memory module of claim 3 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the multiplexer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

6. The memory module of claim 1 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

7. The memory module of claim 1 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

8. The memory module of claim 6 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

9. The memory module of claim 1 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests and coupling the read data to the link interface.

10. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

11. The memory module of claim 1 wherein the memory devices comprises dynamic random access memory devices.

12. The memory module of claim 1 wherein the portion of each of the memory requests generated and coupled by the bypass circuit includes the row address portion of each of the memory requests.

14. The memory hub of claim 12 wherein the status signal comprises:

an active signal indicating that at least one of the memory requests is being serviced; and

an idle signal indicating that at least one of the memory requests is not being serviced.

13. A memory hub, comprising:

a link interface receiving memory requests;

a memory device interface operable to output memory requests, the memory device interface generating a status signal indicating whether or not at least one of the memory requests is being serviced;

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit generating and coupling a portion of each of the memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer generating and coupling the memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is being serviced and generating and coupling the remaining portion of each of the memory requests not handled by the bypass circuit from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.

15. The memory hub of claim 13 wherein the memory hub further comprises a multiplexer having data inputs coupled to the sequencer and the bypass circuit, a data output coupled to the memory device interface and a control input coupled to receive the status signal from the memory device interface, the multiplexer coupling the memory requests from the sequencer responsive to the status signal indicating that at least one of the memory requests is being serviced and coupling a portion of the memory request from the bypass circuit and a portion from the sequencer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

16. The memory hub of claim 13 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.

17. The memory hub of claim 15 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the multiplexer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

18. The memory hub of claim 13 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

19. The memory hub of claim 13 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

20. The memory hub of claim 18 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

21. The memory hub of claim 13 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests and coupling the read data to the link interface.

22. The memory hub of claim 13 wherein the link interface comprises an optical input/output port.

23. The memory hub of claim 13 wherein the memory devices comprises dynamic random access memory devices.

24. The memory hub of claim 13 wherein the portion of each of the memory requests generated and coupled by the bypass circuit includes the row address portion of each of the memory requests.

25. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller; and

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests for access to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface coupling memory requests to the memory devices and generating a status signal indicating whether or not at least one of the memory requests is being serviced;

a bypass circuit coupled to the link interface and the memory device interface, the bypass circuit generating and coupling a portion of each of the memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced; and

a sequencer coupled to the link interface and the memory device interface, the sequencer generating and coupling memory requests from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is being serviced and generating and coupling the remaining portion of each of the memory requests not handled by the bypass circuit from the link interface to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced; and

a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

26. The computer system of claim 26 wherein the status signal comprises:

an active signal indicating that at least one of the memory requests is being serviced; and

an idle signal indicating that at least one of the memory requests is not being serviced.

27. The computer system of claim 26 wherein the memory hub further comprises a multiplexer having data inputs coupled to the sequencer and the bypass circuit, a data output coupled to the memory device interface and a control input coupled to receive the status signal from the memory device interface, the multiplexer coupling the memory requests from the sequencer responsive to the status signal indicating that at least one of the memory requests is being serviced and coupling a portion of the memory request from the bypass circuit and a portion from the sequencer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

28. The computer system of claim 26 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the memory device interface responsive to the status signal from the memory device interface indicating that at least one of the memory requests is not being serviced.

29. The computer system of claim 27 wherein the link interface further receives a link-in clock with each of the memory requests, the link-in clock being forwarded to the bypass circuit along with the memory requests and used by the bypass circuit to generate and couple memory requests to the multiplexer responsive to the status signal indicating that at least one of the memory requests is not being serviced.

30. The computer system of claim 26 wherein the memory device interface comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

31. The computer system of claim 26 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

32. The computer system of claim 30 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

33. The computer system of claim 26 wherein the memory device interface is coupled to the link interface, the memory device interface further receiving read data responsive to the memory requests and coupling the read data to the link interface.

34. The computer system of claim 26 wherein the link interface comprises an optical input/output port.

35. The computer system of claim 26 wherein the memory devices comprises dynamic random access memory devices.

36. The computer system of claim 26 wherein the portion of each of the memory requests generated and coupled by the bypass circuit includes the row address portion of each of the memory requests.

37. The computer system of claim 26 wherein the input and output ports of the system controller comprises a combined input/output port coupled to the communications link, and wherein the input and output ports of each of the memory hubs comprises a combined input/output port coupled to the communications link.

38. The computer system of claim 34 wherein the communications link comprises an optical communications link, wherein the input and output ports of the system controller comprises an optical input/output port coupled to the optical communications link and wherein the input and output ports of each of the memory hubs comprises a respective optical input/output port coupled to the optical communications link.

39. A method of accessing data in each of a plurality of memory devices on each of a plurality of memory modules, each of the memory modules including a memory hub, the method comprising:

checking if a memory device interface located on the memory hub is servicing memory requests;

if the memory device interface is servicing memory requests, sending memory requests through a sequencer located on the memory hub to the memory device interface; and

if the memory device interface is not busy servicing memory requests, sending a portion of each of the memory requests through a bypass circuit located on the memory hub to the memory device interface and the remaining portion of each of the memory requests through the sequencer to the memory device interface.

40. The method of claim 39 wherein the portion of the each of the memory requests sent through the bypass circuit includes the row address portion of each of the memory requests.