Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU
First Claim
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1. An apparatus, comprising:
- a) a high end computing system, said high end computing system further comprising a first central processing unit, said high end system active during a normal active mode; and
b) a low end computing system, said low end computing system further comprising a second central processing unit, said low end computing system having less power consumption than said high end computing system, said low end system active during an active sleep mode, said first central processing unit having a cache, said cache accessible to said second central processing unit.
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Abstract
A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
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Citations
24 Claims
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1. An apparatus, comprising:
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a) a high end computing system, said high end computing system further comprising a first central processing unit, said high end system active during a normal active mode; and
b) a low end computing system, said low end computing system further comprising a second central processing unit, said low end computing system having less power consumption than said high end computing system, said low end system active during an active sleep mode, said first central processing unit having a cache, said cache accessible to said second central processing unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method, comprising:
storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit, said active sleep mode software instructions to be executed by said low end central processing unit during an active sleep mode, said normal active mode software instructions executed by said high end central processing unit during a normal active mode, said active sleep mode consuming less power than said normal active mode. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
Specification