Programming a multi-threaded processor

• US 20040034858A1
• Filed: 08/14/2002
• Published: 02/19/2004
• Est. Priority Date: 08/14/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kushlis, Robert J.
• Application Number:
  US10/219,588
• Publication Number:
  US 20040034858A1
• Time in Patent Office: Days
• US Class Current: 718/108
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A computer instruction includes a declaration instruction that results in a variable name being associated with a memory location in one of a plurality of memories, the declaration instruction having a first field to specify the variable name, a second field to specify a one of the plurality of memory systems to associate with the variable name.

Claims

1. A computer instruction comprises:

a declaration instruction that results in a variable name being associated with a memory location in one of a plurality of memories, the declaration instruction having a first field to specify the variable name, a second field to specify a one of the plurality of memory systems to associate with the variable name.

2. The instruction of claim 1, further comprising:

a third field to declare a pointer corresponding to the location in memory associated with the variable name.

3. The instruction of claim 2, further comprising:

a fourth field to specify a one of the plurality of memories for storing a value corresponding to the pointer.

4. The instruction of claim 1, wherein the instruction results in the variable being replicated for each thread executing in the micro-engine.

5. The instruction of claim 1, further comprising:

a shared specifier that results in the variable declared to be shared by each executable threads on a single micro-engine.

6. The instruction of claim 1, further comprising:

a global specifier that results in the variable declared to be sharable by executable threads on two or more micro-engines.

7. The instruction of claim 1, further comprising:

a transfer register specifier that results in the variable name being associated with a transfer register corresponding to the one of the plurality of memories.

8. The instruction of claim 1, further comprising:

a context synchronization specifier that causes a micro-engine when executing the instruction to determine whether to swap the current thread out of execution.

9. The instruction of claim 8, wherein the determination of whether to swap a context out of execution is based upon a signal from a one of the plurality of memories, the signal used to indicate completion of an operation previously intitiated by the instruction.

10. The instruction of claim 1, further comprising:

a queueing priority specifier that causes a hardware block associated with the one of the plurality of memories to select a received memory access based on the queueing priority specifier.

11. A method of compiling an executable program from a plurality of source code files, the method comprising:

converting each of the plurality of source code files into a corresponding assembly level object file;

linking all of the assembly level object files, wherein linking further comprises;

assembling a graph of at least one of all call instructions and all variable declarations included in the object files before assembling the executable program, and

determining that a first instruction included in a one of the plurality of source code files will cause an access to a one of a plurality of memories included in a processing system.

12. The method of claim 11, further comprising:

selecting a sequence of instructions for execution by a micro-engine that will delay the access to the determined one of the plurality of memories.

13. The method of claim 11, wherein determining further comprises:

determining that the first instruction when executed will access a data value stored in the one of the plurality of memories is followed by at least one subsequent instruction that does not require the data value being accessed by the first instruction; and

selecting the subsequent instruction for execution.

14. The method of claim 11, further comprising:

calculating a pointer value referenced in the first instruction based on an address granularity of the one of the plurality of memories specified by the first instruction.

15. The method of claim 11, wherein determining further comprising:

determining the first instruction includes a context inquiry modifier; and

determining a context number corresponding to the first instruction that may be executed by a micro-engine, wherein the context number is used to determine the flow of execution of the executable program.

16. The method of claim 11, wherein the first instruction includes an export specifier associated with a variable, and a second instruction includes an import specifier associated with the variable, the method further comprises:

using a value associated with the exported variable to determine the value of the imported variable.

17. A storage medium having stored thereon instructions that when executed by a network processor results in the following:

a data item to be read from or written to one of a plurality of memories,

wherein a one of the instructions includes a first field to specify the one of the plurality of memory systems, the instruction also having a second field to declare a variable or a pointer corresponding to the data item.

18. The medium of claim 17, wherein the one of the instructions includes a third field to specify a one of the plurality of memories for storing the variable or pointer declared by the second field.

19. The medium of claim 18, wherein the one of the instructions includes a shared specifier that causes the variable declared to be shared by each executable thread on a single micro-engine.

20. The medium of claim 19, wherein the one of the instructions when accessed by the machine results in the shared variable to be stored in the one of the plurality of memories corresponding to the third specifier.

21. The medium of claim 18, wherein the one of the instructions includes a global specifier that causes the variable declared to be sharable by executable threads on two or more micro-engines.

22. The medium of claim 21, wherein the one of the instructions when executed by the machine results in the global variable to be stored in a one of the plurality of memories, the one of the plurality of memories corresponding to the first specifier included in the instruction.

23. The medium of claim 18, wherein the one of the instructions includes a register specifier that causes the variable to be associated with a location in a register corresponding to a one of the plurality of memories.

24. The medium of claim 18, wherein the one of the instructions includes a context synchronization specifier that causes a micro-engine to determine whether to swap the current thread out of execution.

25. The medium of claim 24, wherein the determination of whether to swap a context out of execution is based upon a signal from a one of the plurality of memories, the signal used to indicate completion of an operation intitiated by a previous instruction in the context.

26. The medium of claim 18, wherein the instruction includes a queueing priority specifier that causes a hardware block associated with the one of the plurality of memories to perform a selection of a received memory access based on the queueing priority specifier.

27. A processing system for executing multiple threads, comprising:

a plurality of multi-threaded micro-engines;

a first memory coupled to the plurality of micro-engines to receive data from and transmit data to the plurality of micro-engines; and

a second memory coupled to the plurality of micro-engines to receive data from and transmit data of the plurality of micro-engines,

wherein one of the plurality of micro-engines executes an instruction that causes an access to one of the first or second memories and also includes sending a queueing priority specifier corresponding to the handling of the memory access.

28. The processing system of claim 27, wherein the access to memory causes a transfer register on the one of the plurality of micro-engines to be associated with the memory access to the one of the memories.