Dual-sided capacitor and method of formation

• US 20040036099A1
• Filed: 05/30/2003
• Published: 02/26/2004
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Er-Xuan Ping, Shenlin Chen
• Original Assignee: Er-Xuan Ping, Shenlin Chen
• Inventors: Ping, Er-Xuan, Chen, Shenlin
• Granted Patent: US 6,858,493 B2
• Time in Patent Office: Days
• US Class Current: 257/297
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Claims

1. A capacitor comprising:

a dual-sided electrode comprising an oxide layer between two conductive layers;

a dielectric layer in contact with said dual-sided electrode; and

a conductive layer over said dielectric layer.

2. The capacitor of claim 1, wherein one of said two conductive layers is a doped polycrystalline layer in contact with said oxide layer.

3. The capacitor of claim 2, wherein the other one of said two conductive layers is a layer of hemispherical grained polysilicon, said oxide layer being located between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

4. The capacitor of claim 1, wherein said oxide layer is a native oxide layer.

5. The capacitor of claim 4, wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

6. The capacitor of claim 2, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

7. The capacitor of claim 6, wherein said doped polycrystalline layer is formed of polysilicon.

8. The capacitor of claim 1, wherein said dual-sided electrode is a lower electrode of said capacitor.

9. The capacitor of claim 1, wherein said dual-sided electrode is an PH₃ annealed dual-sided electrode.

10. The capacitor of claim 1, wherein said oxide layer is an ALD oxide layer.

11. The capacitor of claim 1, wherein said oxide layer is a thermally grown oxide layer.

12. A dual-sided capacitor electrode comprising:

an annealed doped polycrystalline layer having HSG grains of a first thickness; and

a layer of hemispherical grained polysilicon having HSG grains of a second thickness.

13. The dual-sided capacitor electrode of claim 12 further comprising an oxide layer between said annealed doped polycrystalline layer and said layer of hemispherical grained polysilicon.

14. The dual-sided capacitor electrode of claim 13, wherein said oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

15. The dual-sided capacitor electrode of claim 12, wherein said second thickness is greater than said first thickness.

16. The dual-sided capacitor electrode of claim 12, wherein said second thickness is of about 100 Angstroms to about 500 Angstroms.

17. The dual-sided capacitor electrode of claim 12, wherein said first thickness is of about 10 Angstroms to about 50 Angstroms.

18. The dual-sided capacitor electrode of claim 12, wherein said dual-sided electrode is a lower electrode of a capacitor.

19. The dual-sided capacitor electrode of claim 12, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

20. The dual-sided capacitor electrode of claim 12, wherein said doped polycrystalline layer is formed of polysilicon.

21. A memory cell comprising:

a transistor; and

a capacitor including a dual-sided electrode comprising a doped polycrystalline layer, a native oxide layer and a layer of hemispherical grained polysilicon, said dual-sided electrode being electrically connected to one of a source and drain region of said transistor.

22. The memory cell of claim 21, wherein said native oxide layer has a thickness of about 5 Angstroms to about 50 Angstroms.

23. The memory cell of claim 21, wherein said native oxide layer is formed between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

24. The memory cell of claim 21, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

25. The memory cell of claim 21, wherein said dual-sided electrode is a lower electrode.

26. The memory cell of claim 21, wherein said native oxide layer is an ALD oxide layer.

27. The memory cell of claim 21, wherein said native oxide layer is a thermally grown oxide layer.

28. A method of forming a capacitor comprising:

forming a doped polycrystalline layer;

forming a native oxide layer over said doped polycrystalline layer;

forming a layer of hemispherical grained polysilicon over said native oxide layer;

forming a dielectric layer over at least a portion of an outer side of said doped polycrystalline layer and said layer of hemispherical grained polysilicon; and

forming a conductive layer over said dielectric layer.

29. The method of claim 28, wherein said step of forming said dielectric layer further comprises the step of exposing said at least a portion of said outer side of said doped polycrystalline layer.

30. The method of claim 28, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

31. The method of claim 28, wherein said native oxide layer is formed to a thickness of about 5 Angstroms to about 50 Angstroms.

32. The method of claim 28, wherein said native oxide layer is formed between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

33. The method of claim 28, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer.

34. The method of claim 28, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer under a low partial pressure.

35. The method of claim 34, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer for about 1-5 minutes.

36. The method of claim 28, wherein said native oxide layer is thermally grown.

37. The method of claim 28, wherein said native oxide layer is formed by atomic layer deposition.

38. The method of claim 28, wherein said act of forming said layer of hemispherical grained polysilicon further comprises depositing an amorphous layer of polysilicon over said native oxide layer.

39. The method of claim 38 further comprising annealing said amorphous layer of polysilicon to form said layer of hemispherical grained polysilicon.

40. The method of claim 39, wherein said anneal is a PH₃ anneal.

41. A method of forming a dual-sided capacitor comprising:

forming an opening in an insulating layer;

forming a doped polysilicon layer within said opening;

forming a native oxide layer over said doped polysilicon layer;

forming a layer of hemispherical grained polysilicon over said native oxide layer;

removing at least a portion of said insulating layer to expose at least a portion of an outer side of said doped polysilicon layer;

forming a layer comprising a high-dielectric constant material over said exposed portion of said doped polysilicon layer and over said layer of hemispherical grained polysilicon; and

forming a conductive layer over said layer comprising a high-dielectric constant material.

42. The method of claim 41, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer.

43. The method of claim 41, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure.

44. The method of claim 43, wherein said low partial pressure is of about 10⁻

6 Torr.

45. The method of claim 43, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure of about 10⁻

6 Torr and for about 1-5 minutes.

46. The method of claim 41, wherein said native oxide layer is thermally grown.

47. The method of claim 41, wherein said native oxide layer is formed by atomic layer deposition.

48. The method of claim 41, wherein said act of forming said layer of hemispherical grained polysilicon further comprises depositing an amorphous layer of polysilicon over said native oxide layer.

49. The method of claim 48 further comprising annealing said amorphous layer of polysilicon to form said layer of hemispherical grained polysilicon.

50. The method of claim 49, wherein said anneal is a PH₃ anneal.