Semiconductor device and a method of producing the same

• US 20040036121A1
• Filed: 08/07/2003
• Published: 02/26/2004
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tsuzuki, Yukio, Aoki, Takaaki
• Granted Patent: US 7,126,187 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a cell region in a surface portion of the substrate for operating as a transistor;

a gate lead wiring region having a gate lead pattern on the substrate;

a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region;

an oxide film on an inner surface of the trench so as to have sidewalls and a bottom wall; and

a gate electrode in the trench insulated with at least the oxide film from the substrate,

wherein the oxide film is provided by thermal oxidation of a portion of the substrate at a position corresponding thereto,

wherein a speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, and

wherein a thickness of the oxide film on the main portion of the sidewalls of the trench at the gate lead wiring region is greater than that at the cell region.

2. The semiconductor device according to claim 1,

wherein the semiconductor substrate includes a silicon substrate having a (100) crystal plane or its equivalent planes,

wherein the main portion of the sidewalls of the trench at the cell region includes the (100) crystal plane or its equivalent planes, and

wherein the main portion of the sidewalls of the trench at the gate lead wiring region includes a (110) crystal plane or its equivalent planes.

3. The semiconductor device according to claim 1,

wherein the semiconductor substrate includes a silicon substrate having a (110) crystal plane or its equivalent planes,

wherein the main portion of the sidewalls of the trench at the cell region includes a (100) crystal plane or its equivalent plane, and

wherein the main portion of the sidewalls of the trench at the gate lead wiring region includes the (110) crystal plane or its equivalent planes.

4. The semiconductor device according to claim 1,

wherein the semiconductor substrate includes a silicon substrate having a (110) crystal plane or its equivalent planes,

wherein the main portion of the sidewalls of the trench at the cell region includes a (100) crystal plane or its equivalent planes, and

wherein the main portion of the sidewalls of the trench at the gate lead wiring region includes a (111) crystal plane or its equivalent planes.

5. The semiconductor device according to claim 1,

wherein the trench at the cell region provides a quadrangle cell, and

wherein a plurality of cells is arranged on the surface of the substrate like a net pattern at the cell region.

6. The semiconductor device according to claim 1,

wherein the trench at the cell region provides a hexagon cell, and

wherein a plurality of cells is arranged on the surface of the substrate like a net pattern at the cell region.

7. The semiconductor device according to claim 1,

wherein the trench at the cell region provides an octagon cell as a first cell and a quadrangle cell as a second cell, and

wherein a plurality of first and second cells is arranged on the surface of the substrate like a net pattern at the cell region in such a manner that the first and second cells are alternately arranged.

8. The semiconductor device according to claim 2,

wherein the trench at the cell region provides a quadrangle cell,

wherein a plurality of cells is arranged on the surface of the substrate like a net pattern at the cell region, and

wherein all sidewalls of the trench in each cell includes the (100) crystal plane or its equivalent planes.

9. The semiconductor device according to claim 2,

wherein the trench at the cell region provides a hexagon cell,

wherein a plurality of cells is arranged on the surface of the substrate like a net pattern at the cell region,

wherein four sidewalls of the trench in each cell includes the (100) crystal plane or its equivalent planes, and

wherein the remaining two sidewalls of the trench in each cell includes the (110) crystal plane or its equivalent planes.

10. The semiconductor device according to claim 9,

wherein each of the four sides of the hexagon cell is longer than each of the remaining two sides of the hexagon cell.

11. The semiconductor device according to claim 10,

wherein the trench has a predetermined width on a surface of the substrate, and

wherein a length of each of the remaining two sides of the hexagon cell is substantially the same as the predetermined width.

12. The semiconductor device according to claim 11,

wherein the length of each of the remaining two sides is in a range between 0.5 μ

m and 1.0 μ

m.

13. The semiconductor device according to claim 1,

wherein a plurality of trenches extends from the cell region to the gate lead wiring region in such a manner that each end of the trenches at the gate lead wiring region does not connect together.

14. The semiconductor device according to claim 1,

wherein a plurality of trenches extends from the cell region to the gate lead wiring region in such a manner that each end of the trenches at the gate lead wiring region connects together.

15. The semiconductor device according to claim 1,

wherein the trench at the cell region provides a hexagon cell,

wherein a plurality of cells is arranged on the surface of the substrate like a net pattern at the cell region,

wherein each of four sides of the hexagon cell extends in a direction making an angle of 120°

with a <

110>

crystal axis, and

wherein each of the remaining two sides of the hexagon cell extends along the <

110>

crystal axis.

16. The semiconductor device according to claim 3,

wherein the trench at the cell region provides a hexagon cell,

wherein a plurality of cells is arranged on the surface of the semiconductor substrate like a net pattern at the cell region,

wherein two sides of the hexagon cell extend along a <

100>

crystal axis,

wherein the remaining four sides of the hexagon cell extend along a <

111>

crystal axis, and

wherein a total length of the two sides is equal to or greater than a total length of the remaining four sides.

17. A method of producing a semiconductor device, comprising the steps of:

forming a trench in a surface portion of a semiconductor substrate so as to extend from a cell-to-be-formed region for forming a cell for operating as a transistor to a gate-lead-wiring-to-be-formed region;

forming an oxide film on an inner surface of the trench so as to have sidewalls and a bottom wall by thermal oxidation; and

forming a gate electrode in the trench insulated with at least the oxide film from the substrate,

wherein, in the step of forming the trench, the trench is formed to have crystal planes of a first main portion of the sidewalls of the trench at the cell-to-be-formed region and a second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region in such a manner that a first speed of forming the oxide film at the cell-to-be-formed region is smaller than a second speed of forming the oxide film at the gate-lead-wiring-to-be-formed region, and

wherein, in the step of forming the oxide film, the thermal oxidation is performed so as to make a first thickness of the oxide film on the inner surface of the trench at the cell-to-be-formed region thinner than a second thickness of the oxide film on the inner surface of the trench at the gate-lead-wiring-to-be-formed region.

18. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (100) crystal plane,

wherein the first main portion of the sidewalls of the trench at the cell-to-be-formed region has the (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has a (110) crystal plane.

19. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (110) crystal plane,

wherein the first main portion of the sidewalls of the trench at the cell-to-be-formed region has a (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has the (110) crystal plane.

20. The method according to claim 17,

wherein the substrate includes a silicon substrate having a (110) crystal plane,

wherein the first main portion of the sidewalls of the trench at the cell-to-be-formed region has a (100) crystal plane, and

wherein the second main portion of the sidewalls of the trench at the gate-lead-wiring-to-be-formed region has a (111) crystal plane.

21. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a quadrangle cell, and

wherein a plurality of cells is arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

22. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a hexagon cell, and

wherein a plurality of cells is arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

23. The method according to claim 17,

wherein the trench at the cell-to-be-formed region provides a octagon cell as a first cell and a quadrangle cell as a second cell, and

wherein a plurality of first and second cells is alternately arranged on the surface of the semiconductor substrate like a net pattern at the cell region.

24. The method according to claim 18,

wherein, in the step of forming the oxide film, the thermal oxidation is performed at a temperature between 850°

C. and 1000°

C.

25. A semiconductor device comprising:

a semiconductor substrate;

a transistor in a surface portion of the substrate at a cell region, the transistor including a first trench in the surface potion extending along the surface of the substrate and a first oxide film on an inner surface of the first trench so as to have first sidewalls and a first bottom wall;

a gate lead wiring pattern on the substrate at a gate lead wiring region, which is dispose outside of the cell region;

a second trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, the second trench including a second oxide film on an inner surface of the second trench so as to have second sidewalls and a second bottom wall; and

first and second gate electrodes in the first and second trenches insulated with at least the first and second oxide films from the semiconductor substrate, respectively, the first gate electrode being electrically connected to the gate lead wiring pattern through the second gate electrode,

wherein the first and second oxide films are provided by thermal oxidation of the first and second sidewalls and the first and second bottom walls of the first and second trenches, respectively, and

wherein a thickness of the oxide film on the second sidewall is greater than that on the first sidewall.

26. A semiconductor device comprising:

a semiconductor substrate;

a cell region in a surface portion of the substrate for operating as a transistor;

a gate lead wiring region having a gate lead pattern on the substrate;

a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region;

an oxide film on an inner surface of the trench so as to have sidewalls and a bottom wall; and

a gate electrode in the trench insulated with at least the oxide film from the substrate,

wherein a thickness of the oxide film on a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that at the cell region,

wherein the main portion of the sidewalls of the trench at the cell region includes a first crystal plane or its equivalent planes,

wherein the main portion of the sidewalls of the trench at the gate lead wiring region includes a second crystal plane or its equivalent planes, and

wherein a speed of formation of the oxide film on the first crystal plane is greater than that on the second crystal plane.

27. The semiconductor device according to claim 26,

wherein the semiconductor substrate includes a silicon substrate having a (100) crystal plane or its equivalent planes,

wherein the first crystal plane includes the (100) crystal plane or its equivalent planes, and

wherein the second crystal plane includes a (110) crystal plane or its equivalent planes.

28. The semiconductor device according to claim 26,

wherein the semiconductor substrate includes a silicon substrate having a (110) crystal plane or its equivalent planes,

wherein the first crystal plane includes the (100) crystal plane or its equivalent planes, and

wherein the second crystal plane includes a (110) crystal plane or its equivalent planes.

29. The semiconductor device according to claim 26,

wherein the semiconductor substrate includes a silicon substrate having a (110) crystal plane or its equivalent planes,

wherein the first crystal plane includes the (100) crystal plane or its equivalent planes, and

wherein the second crystal plane includes a (111) crystal plane or its equivalent planes.