Multi-gate carbon nano-tube transistors

• US 20040036128A1
• Filed: 03/28/2003
• Published: 02/26/2004
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhang, Yuegang, Doyle, Brian S., Bourianoff, George I.
• Granted Patent: US 6,972,467 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

According to one aspect of the invention, a semiconducting transistor is described. The channel portion of the transistor includes carbon nanotubes formed on top of an insulating layer which covers a local bottom gate. Source and drain conductors are located at ends of the carbon nanotubes. A gate dielectric surrounds a portion of the carbon nanotubes with a substantially uniform thickness. A local top gate is located between the source and drain conductors over the carbon nanotubes. Lower portions of the local top gate are positioned between the carbon nanotubes as the local top gate forms pi-gates or “wraparound” gates around each carbon nanotube.

Claims

1. A semiconductor device, comprising:

a substrate;

source and drain conductors on the substrate;

a semiconducting carbon nanotube interconnecting the source and the drain conductors, the semiconducting carbon nanotube, in at least one cross-section transverse through an elongate axis of the semiconducting carbon nanotube, having opposing sides;

a plurality of gate dielectric portions, each gate dielectric portion being adjacent to one of the opposing sides of the semiconducting carbon nanotube; and

a plurality of gate electrodes, in the cross-section, being electrically disconnected from one another, at least one gate electrode being adjacent to each of the insulators, the gate electrodes located such that when a voltage is applied to the gate electrodes, the source and the drain conductors are electrically coupled through the semiconducting carbon nanotube.

2. The semiconductor device of claim 1, wherein the substrate is at least one of an insulating substrate and a semiconducting substrate.

3. The semiconductor device of claim 2, wherein the substrate is silicon.

4. The semiconductor device of claim 3, wherein the source and the drain conductors have a distance between them of approximately 800 nm and a thickness of 300 nm.

5. The semiconductor device of claim 4, wherein the source and the drain conductors are at least one of tungsten, titanium, gold, aluminum, and copper.

6. The semiconductor device of claim 5, wherein the semiconducting carbon nanotube has source and drain ends and a channel portion, the source and the drain ends being at opposing sides of the channel portion.

7. The semiconductor device of claim 6, wherein the source conductor is formed adjacent to the source end of the semiconducting carbon nanotube and the drain conductor is formed adjacent to the drain end of the semiconducting carbon nanotube.

8. The semiconductor device of claim 7, wherein the semiconducting carbon nanotube is a single-walled carbon nanotube.

9. The semiconductor device of claim 8, wherein the semiconducting carbon nanotube is cylindrical with a diameter of approximately 2 nm and a length of 750 nm and has a curved outer surface.

10. The semiconductor device of claim 9, further comprising a catalyst deposited on a surface of the one of the insulators adjacent to the semiconducting carbon nanotube.

11. The semiconductor device of claim 10, wherein the catalyst is at least one of iron, cobalt, and nickel.

12. The semiconductor device of claim 11, wherein the semiconducting carbon nanotube is chemically bonded to the catalyst.

13. The semiconductor device of claim 12, wherein the gate dielectric portions are high capacitance gate dielectric portions.

14. The semiconductor device of claim 13, wherein the gate dielectric portions are at least one of zirconium oxide and silicon oxide.

15. The semiconductor device of claim 14, wherein one of the gate dielectric portions is adjacent to the curved outer surface of the semiconducting carbon nanotube and has a portion with a substantially uniform thickness.

16. The semiconductor device of claim 15, wherein the gate electrodes are at least one of tungsten, titanium, gold, aluminum, and copper and have a thickness of 300 nm.

17. The semiconductor device of claim 16, wherein one of the gate electrodes is around only the portion of the one insulator with a substantially uniform thickness.

18. A semiconductor device, comprising:

source and drain conductors;

a plurality of semiconducting carbon nanotubes interconnecting the source and drain conductors in parallel, each semiconducting nanotube having at least two sides;

a plurality of insulating bodies each being adjacent to a respective side of a respective semiconducting carbon nanotube; and

a plurality of gate electrodes each being adjacent to a respective insulating body, the gate electrodes located such that when a voltage is applied to the gate electrodes, the source and the drain conductors are electrically coupled through the semiconducting carbon nanotubes.

19. The semiconductor device of claim 18, wherein the semiconducting carbon nanotubes are positioned such that elongate axes of the semiconducting carbon nanotubes are substantially parallel to an upper surface of the substrate.

20. The semiconductor device of claim 19, wherein the semiconducting carbon nanotubes are aligned in a column that is substantially perpendicular to the upper surface of the substrate.

21. A semiconductor device, comprising:

a substrate;

source and drain conductors on the substrate;

a semiconducting carbon nanotube interconnecting the source and the drain conductors, the semiconducting carbon nanotube having a curved outer surface;

an insulator being adjacent to the curved outer surface of the semiconducting carbon nanotube, only a portion of the insulator having a curved outer insulator surface; and

a gate electrode being adjacent to the curved outer insulator surface of the insulating body and around only a portion of the insulating body.

22. The semiconductor device of claim 21, the gate electrode is a local top gate electrode.

23. The semiconductor device of claim 22, wherein a plurality of semiconducting carbon nanotubes interconnect the source and the drain conductors, each semiconducting carbon nanotube positioned such that an entire length of an elongate axis of each semiconducting carbon nanotubes is at substantially uniform distance from an upper surface of the substrate and wherein the portion of the insulator with the curved outer insulator surface has a substantially uniform thickness.

24. The semiconductor device of claim 23, wherein the gate electrode has a plurality of lower portions that extend between the plurality of semiconducting carbon nanotubes.

25. A semiconductor device, comprising:

a substrate;

at least one local bottom gate electrode formed on the substrate;

a first insulator formed on the local bottom gate electrodes;

a semiconducting carbon nanotube formed on the first insulating body, the semiconducting carbon nanotube having source and drain ends and a channel portion, the source and drain ends being at opposing sides of the channel portion;

source and drain conductors, the source conductor being adjacent to the source portion of the semiconducting carbon nanotube, the drain conductors being adjacent to the drain portion of the semiconducting carbon nanotube, the semiconducting carbon nanotube interconnecting the source and drain conductors;

a second insulator formed on the semiconducting carbon nanotube; and

at least one local top gate electrode formed on the second insulator, the local bottom and top gates electrically disconnected from the semiconducting carbon nanotube and the source and drain conductors, the local bottom and top gate electrodes located such that when a voltage is applied to the local bottom and top gate electrodes, the source and the drain conductors are electrically coupled through the semiconducting carbon nanotube.

26. The semiconductor device of claim 25, further comprising a plurality of local bottom gates and a plurality of local top gates, the local bottom gates being electrically disconnected from one another, the local top gates being electrically disconnected from one another.

27. The semiconductor device of claim 26, wherein the plurality of local bottom and top gates are arranged in a plurality of gate pairs, each pair comprising a local bottom gate and a local top gate, each gate electrode in a pair directly opposing the other gate electrode in the pair.

28. A method for constructing a semiconductor transistor, comprising:

forming a local bottom gate electrode on a substrate;

forming an insulating layer on the bottom gate electrode;

positioning a semiconducting carbon nanotube on the insulating layer over the local bottom gate electrode, the semiconducting carbon nanotube having an elongate axis, source and drain ends, and a channel portion between the source and drain ends;

forming source and drain conductors over the respective source and drain ends of the semiconducting carbon nanotube;

forming a gate dielectric on the source and drain conductors and the channel portion of the semiconducting carbon nanotube; and

forming a local top gate electrode over the channel portion of the semiconducting carbon nanotube, the local top gate electrode, in at least one cross-section transverse to the elongate axis of the semiconducting carbon nanotube, being electronically disconnected from the local bottom gate electrode, the local bottom gate electrode and the local top gate electrode being located such that when a voltage is applied to the local top and bottom gate electrodes, the source and drain conductors electrically coupled through the semiconducting carbon nanotube.

29. The method of claim 28, wherein the semiconducting carbon nanotube has a curved outer surface, the gate dielectric being adjacent to the curved outer surface of the semiconducting nanotube, only a portion of the gate dielectric having a curved outer gate dielectric surface.

30. The method of claim 29, wherein the portion of the gate dielectric with the curved outer gate dielectric surface has a substantially uniform thickness.