Atomic layer deposition of CMOS gates with variable work functions
First Claim
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1. A transistor, comprising:
- a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition.
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Abstract
Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.
594 Citations
59 Claims
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1. A transistor, comprising:
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a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A vertical multistate cell, comprising:
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a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;
a sourceline coupled to the source region; and
a transmission line coupled to the drain region. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A vertical multistate cell, comprising:
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a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Tantalum Aluminum Nitride (TaAlN) layer;
a wordline coupled to the gate;
a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and
a bit line coupled to the drain region. - View Dependent Claims (14, 15, 16, 20)
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17. A vertical multistate cell, comprising:
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a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Titanium Aluminum Nitride (TiAlN) layer;
a wordline coupled to the gate;
a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and
a bit line coupled to the drain region. - View Dependent Claims (18, 19)
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21. A vertical multistate cell, comprising:
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a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Titanium Silicon Nitride (TiSiN) layer;
a wordline coupled to the gate;
a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and
a bit line coupled to the drain region. - View Dependent Claims (22, 23, 24)
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25. A vertical multistate cell, comprising:
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a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Tungsten Aluminum Nitride (WAlN) layer;
a wordline coupled to the gate;
a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and
a bit line coupled to the drain region. - View Dependent Claims (26, 27, 28)
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29. A transistor array, comprising:
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a number of transistor cells formed on a substrate, wherein each transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;
a number of bit lines coupled to the drain region of each transistor cell along rows of the transistor array;
a number of word lines coupled to the gate of each transistor cell along columns of the memory array; and
a number of sourcelines, wherein the source region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A semiconductor device, comprising:
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a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;
a number of bit lines coupled to the drain region of each transistor along rows of the memory array;
a number of word lines coupled to the gate of each transistor along columns of the memory array;
a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench;
a wordline address decoder coupled to the number of wordlines;
a bitline address decoder coupled to the number of bitlines; and
a sense amplifier coupled to the number of bitlines. - View Dependent Claims (36, 37, 38, 39, 40, 41)
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42. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, wherein the memory device includes;
a memory array, wherein the memory array includes a number of transistor cells formed on a substrate, wherein each transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;
a number of bit lines coupled to the drain region of each transistor cell along rows of the transistor array;
a number of word lines coupled to the gate of each transistor cell along columns of the memory array; and
a number of sourcelines, wherein the source region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells. - View Dependent Claims (43, 44, 45, 46, 47)
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48. A method for forming a transistor, comprising:
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forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;
forming a gate opposing the channel region and separated therefrom by a first gate insulator; and
wherein forming the gate includes forming a ternary metallic conductor by atomic layer deposition. - View Dependent Claims (49, 50, 51, 52, 53)
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54. A transistor pair, comprising:
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a PMOS transistor;
an NMOS transistor;
wherein the NMOS and the PMOS transistor each include a source, a drain, a channel region therebetween, a gate separated from the channel region by a gate insulator; and
wherein the gates of the NMOS and the PMOS transistors include a varied composition and a varied work function to achieve a low threshold voltages of a same magnitude. - View Dependent Claims (55, 56, 57, 58)
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59. A method for forming a transistor pair, comprising:
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forming a PMOS transistor;
forming an NMOS transistor; and
wherein forming the NMOS and the PMOS transistors includes forming a varied gate composition having a varied work function on each respective transistor in order to control a threshold voltage for each respective transistor to a same magnitude.
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Specification