Clock receiver circuit for on-die salphasic clocking

• US 20040036520A1
• Filed: 08/29/2003
• Published: 02/26/2004
• Est. Priority Date: 08/29/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Ram K., Soumyanath, Krishnamurthy, Anders, Mark A.
• Granted Patent: US 6,828,841 B2
• Time in Patent Office: Days
• US Class Current: 327/298
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Claims

1. A clock receiver circuit comprising:

first and second differential input nodes to receive first and second differential input signals from a clock distribution medium;

a differential amplifier to amplify a difference between the first and second differential input signals to generate first and second amplified differential signals; and

an output stage to generate an output clock signal using the first and second amplified differential signals.

2. The clock receiver circuit of claim 1 wherein:

said differential amplifier includes a folded cascode differential amplifier.

3. The clock receiver circuit of claim 1 wherein:

said first and second differential input signals are sinusoidal signals.

4. The clock receiver circuit of claim 1 wherein:

said output clock signal has an amplitude that is at least three times an amplitude of said first and second differential input signals.

5. The clock receiver circuit of claim 1 wherein:

said output stage generates a square wave output clock signal that alternates between first and second supply voltages.

6. The clock receiver circuit of claim 1 wherein:

said first and second differential input nodes receive said first and second differential input signals from a salphasic clock distribution medium.

7. The clock receiver circuit of claim 6 wherein:

said clock receiver circuit and said salphasic clock distribution medium are implemented on a common microelectronic die.

8. A microelectronic die comprising:

a clock distribution medium having first and second differential signal lines, said first differential signal line to carry a first differential signal component and said second differential signal line to carry a second differential signal component; and

a clock receiver circuit coupled to said first and second differential signal lines to generate an output clock signal using said first and second differential signal components, said clock receiver circuit including a differential amplifier to amplify a difference between said first and second differential signal components.

9. The microelectronic die of claim 8 wherein:

said differential amplifier includes a folded cascode differential amplifier.

10. The microelectronic die of claim 8 wherein:

said differential clock distribution medium is part of a salphasic clock distribution network

11. The microelectronic die of claim 8 wherein:

said clock receiver circuit includes a single amplification stage.

12. The microelectronic die of claim 8 wherein:

said first and second differential signal components are sinusoidal.

14. The microelectronic die of claim 8 wherein:

said clock receiver circuit includes an output portion to generate a full swing, square wave output clock that alternates between first and second supply potentials.

16. The microelectronic die of claim 8 wherein:

said microelectronic die is part of a microprocessor unit.

13. The microelectronic die of claim 13 wherein:

said output clock signal is a square wave.

15. The microelectronic die of claim 15 wherein:

said output portion of said clock receiver circuit uses a reduced Vcc level to generate said output clock to conserve clock power.

17. A microelectronic die comprising:

a differential clock distribution medium having first and second differential signal lines, said first differential signal line to carry a first differential signal component and said second differential signal line to carry a second differential signal component;

a first clock receiver circuit to generate a true clock signal, said first clock receiver circuit having a positive differential clock input and a negative differential clock input, said positive differential clock input coupled to said first differential signal line and said negative differential clock input coupled to said second differential signal line; and

a second clock receiver circuit to generate a complement clock signal, said second clock receiver circuit having a positive differential clock input and a negative differential clock input, said positive differential clock input coupled to said second differential signal line and said negative differential clock input coupled to said first differential signal line.

18. The microelectronic die of claim 18 wherein:

said first and second clock receiver circuits have substantially the same circuit architecture.

19. The microelectronic die of claim 18 wherein:

said first clock receiver circuit includes a folded cascode differential amplifier.

21. The microelectronic die of claim 18 wherein:

said first and second differential signal components are sinusoidal and said true and complement clock signals are square waves.

22. The microelectronic die of claim 18 wherein:

said differential clock distribution medium is part of a salphasic clock distribution network.

23. The microelectronic die of claim 18 wherein:

said microelectronic die is part of a microprocessor unit.

20. The microelectronic die of claim 20 wherein:

said second clock receiver circuit includes a folded cascode differential amplifier.