Wide dynamic range linear-and-log active pixel

• US 20040036785A1
• Filed: 08/23/2002
• Published: 02/26/2004
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Takayanagi, Isao
• Granted Patent: US 7,443,427 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/573 the logarithmic type
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A pixel circuit having an improved dynamic range is disclosed. When incoming light detected by the photodiode is strong, the accumulated (integrated) charge on a signal capacitor becomes large. To compensate, the excess signal component becomes compressed and the pixel circuit begins operating in logarithmic rather than linear mode. In this way, the circuit can achieve a higher dynamic range more closely resembling the image sensing properties of the human eye.

Claims

1. A pixel circuit, comprising:

a photoconversion device for accumulating charge during a charge integration period, one leg of said photo conversion device being connected to an integration node;

a first transistor, having one of a source and drain terminal connected to said integration node and the other of a drain and source terminal connected to a reset line;

said first transistor operating during said charge integration period in a first mode to provide a linear accumulation of charge by said photoconversion device up to a predetermined charge level, and in a second mode to provide a logarithmic accumulation of charge by said photoconversion device after said predetermined charge level is reached.

2. The pixel circuit of claim 1, further comprising:

a feed-through pulse capacitor, having one leg connected to an feed-through pulse signal line, and the other leg connected to said integration node.

3. The pixel circuit of claim 1, further comprising:

an output circuit, connected to said integration node, for reading out a signal at said integration node.

4. The pixel circuit of claim 3, wherein said output circuit further comprises an output transistor operating as a source follower readout transistor.

5. The pixel circuit of claim 1, wherein said first mode is an shut-off mode and said second mode is a sub-threshold mode.

6. The pixel circuit of claim 5, further comprising:

wherein said first transistor switches from said first mode to said second mode when a voltage at said integration node exceeds a voltage applied to a gate of said first transistor minus a threshold voltage.

7. The pixel circuit of claim 1, wherein said photoconversion device is a photodiode.

8. The pixel circuit of claim 7, wherein one of the source and drain regions of said first transistor is connected to a reset signal line, and the other of said source and drawing regions is connected to said integration node, and a gate of the first transistor is connected to a supply voltage.

9. The pixel circuit of claim 8, further comprising:

a capacitor having one terminal connected to said integration node and another terminal connected to a feed through pulse line.

10. The pixel circuit of claim 9, wherein said reset signal line and said feed through pulse line are operable to apply a reset voltage to said integration node.

11. The pixel circuit of claim 10, further comprising:

an output circuit and a pixel select line for operating said output circuit to read out said reset voltage to an output line.

12. The pixel circuit of claim 11 wherein said pixel select line is operable to begin a charge integration period.

13. A CMOS imaging device, comprising:

at least one pixel circuit;

a sample and hold circuit for storing a reset signal and an image signal produced by said pixel circuit;

an amplifier for subtracting the reset signal and image signal;

a digitizer for receiving the output of said amplifier; and

an image processor for receiving the output of said digitizer;

wherein said pixel circuit further comprises;

a photoconversion device for accumulating charge during a charge integration period, one leg of said photo conversion device being connected to an integration node;

a first transistor, having one of a source and drain terminal connected to said integration node and the other of a drain and source terminal connected to a reset line;

said first transistor operating during said charge integration period in a first mode to provide a linear accumulation of charge by said photoconversion device up to a predetermined charge level, and in a second mode to provide a logarithmic accumulation of charge by said photoconversion device after said predetermined charge level is reached.

14. The pixel circuit of claim 13, further comprising:

a feed-through pulse capacitor, having one leg connected to an feed-through pulse signal line, and the other leg connected to said integration node.

15. The pixel circuit of claim 13, further comprising:

an output circuit, connected to said integration node, for reading out a signal at said integration node.

16. The pixel circuit of claim 15, wherein said output circuit further comprises an output transistor operating as a source follower readout transistor.

17. The pixel circuit of claim 13, wherein said first mode is an shut-off mode and said second mode is a sub-threshold mode.

18. The pixel circuit of claim 17, further comprising:

wherein said first transistor switches from said first mode to said second mode when a voltage at said integration node exceeds a voltage applied to a gate of said first transistor minus a threshold voltage.

19. The pixel circuit of claim 13, wherein said photoconversion device is a photodiode.

20. The pixel circuit of claim 19, wherein one of the source and drain regions of said first transistor is connected to a reset signal line, and the other of said source and drawing regions is connected to said integration node, and a gate of the first transistor is connected to a supply voltage.

21. The pixel circuit of claim 20, further comprising:

a capacitor having one terminal connected to said integration node and another terminal connected to a feed through pulse line.

22. The pixel circuit of claim 21, wherein said reset signal line and said feed through pulse line are operable to apply a reset voltage to said integration node.

23. The pixel circuit of claim 22, further comprising:

an output circuit and a pixel select line for operating said output circuit to read out said reset voltage to an output line.

24. The pixel circuit of claim 23, wherein said pixel select line is operable to begin a charge integration period.

25. A method of operating a pixel circuit, comprising:

collecting photogenerated charge at an integration node in response to a pixel signal during a charge integration period;

operating a first transistor in an shut-off mode during said integration period when the amount of said collected charge is below a threshold value to cause charge to be linearly collected at said node; and

operating said first transistor in a sub-threshold mode during said integration period when said collected charge is above said threshold to cause charge to be logarithmically collected at said node.

26. The method of claim 25, further comprising:

prior to a reset operation, injecting charge into a pixel capacitor thereby pinning said pixel capacitor at a low level of a reset line.

27. The method of claim 25, further comprising:

during the time said first transistor is operating in a sub-threshold mode, draining excess charge from said integration node through a conversion transistor thereby completely discharging an integration capacitor connected to said integration node.

28. The method of claim 27, further comprising:

separating said accumulated charge into color and brightness components;

processing said color component; and

recombining said brightness and color components.

29. The method of claim 28, further comprising:

during the time said accumulated charge is collected logarithmically, dividing said logarithmic charge-accumulation phase into first and second logarithmic phases corresponding to lower and higher saturation levels respectively; and

during exposure of said circuit to high saturation levels, standardizing the output voltage of said circuit.

30. The method of claim 29, further comprising:

during said second logarithmic phase, eliminating a color signal from the output of said pixel.

31. The method of claim 29, further comprising:

during said second logarithmic phase, setting a color signal from the output of said pixel to a predetermined minimum value.

32. A pixel circuit comprising:

a photoconversion device;

an integration node, connected to said photoconversion device;

a conversion transistor, for accumulating charge from said photoconversion device onto said integration node;

a signal controller, connected to said pixel circuit, for controlling the resetting, signal accumulation, and reading out of said circuit;

a selection transistor, responsive to said signal controller, for selecting when said integration node is to be read out;

a readout circuit, responsive to said signal controller, for reading out said integration node;

an integration capacitor, for accumulating charge at said integration node;

a feed through pulse line, connected to said signal controller and said integration capacitor;

a reset line, connected to said signal controller and said conversion transistor;

a read line, connected to said signal controller and said readout circuit; and

a voltage supply line, connected to said accumulation transistor and also said readout circuit.

33. The pixel circuit of claim 32, further comprising:

said photoconversion device being a photodiode.