Apparatus for inspecting wafer surface, method for inspecting wafer surface, apparatus for judging defective wafer, method for judging defective wafer, and apparatus for processing information on wafer surface

• US 20040036863A1
• Filed: 08/25/2003
• Published: 02/26/2004
• Est. Priority Date: 09/05/2000
• Status: Active Grant

• Current Assignee: Sumco Techxiv Kabushiki Kaisha
• Original Assignee: Sumco Techxiv Kabushiki Kaisha
• Inventors: Matsumura, Yukinori, Miyakawa, Kiyoharu, Hori, Kotaro, Nisi, Akira, Tanuki, Tomikazu, Miwa, Hirobumi, Terada, Mitsuo, Matsusita, Kouzou
• Granted Patent: US 7,383,156 B2
• Time in Patent Office: Days
• US Class Current: 356/237.2
• CPC Class Codes: G01N 2021/8861 Determining coordinates of flaws
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

It is possible to inspect scratches and staining on a wafer surface on the basis of an LPD map obtained from a particle counter 11, by providing a means 21 for detecting aggregation of clustered point defects (LPD) from two-dimensional distribution information 30 for such fine LPD on the surface of a silicon wafer, and an improvement in the inspection efficiency and the precision of judgements of “defective” status can be achieved. Furthermore, the system is devised so that the trend of generation of scratches and staining in a specified process can easily be detected by accumulating wafer surface information such as scratch information, staining information and the like for the wafer surface detected by a wafer surface inspection device 11 (especially as image information or numerical information), and superposing sets of information thus accumulated. Plans for improving processes can be made by both the wafer supplier and wafer consumer by sharing such information with both parties.

Claims

1. A wafer surface inspection device which detects scratches on a wafer surface on the basis of two-dimensional defect distribution information (an LPD map) for the wafer surface supplied from a particle counter, comprising:

input means for inputting the LPD map supplied from the particle counter;

memory means capable of accumulating the LPD map for each of a plurality of wafers; and

information processing means for detecting the scratches on the wafer surface by detecting the cluster of LPD in the LPD maps accumulated in the memory means.

2. The wafer surface inspection device according to claim 1, characterized in that the information processing means detects defects (scratch defects) by detecting aggregation of linearly clustered LPD by means of two-dimensional half-conversion processing for each partial area of the LPD map.

3. The wafer surface inspection device according to claim 1, characterized in that the information processing means further detects indefinite-form aggregation of LPD as defects (staining defects) in distinction from surrounding areas by smoothing at least a portion of the LPD map by means of a space filter, and binarizing the result of smoothing with a specified threshold value.

4. A wafer surface inspection method for detecting scratches on a wafer surface on the basis of two-dimensional defect distribution information (an LPD map) for the wafer surface supplied from a particle counter, characterized in that the method comprises a step of detecting the cluster of LPD in the LPD map extracted from the wafer surface to detect the scratches on the wafer surface.

5. The wafer surface inspection method according to claim 4, characterized in that, in the step of detecting defects, the defects (scratch defects) are detected by detecting aggregation of linearly clustered LPD by means of two-dimensional half-conversion processing for each partial area of the LPD map.

6. The wafer surface inspection method according to claim 4, further comprising a step of detecting indefinite-form aggregation of the LPD as defects (staining defects) in distinction from surrounding areas by smoothing at least a portion of the LPD map by means of a space filter, and binarizing the result of smoothing with a specified threshold value.

7. A computer-readable memory medium which accommodates a program that includes a detection step of detecting scratches on a wafer surface by detecting the cluster of LPD on the basis of two-dimensional defect distribution information (an LPD map) extracted from the wafer surface.

8. A judgement device which judges whether or not a wafer that has scratches and staining on its surface is acceptable as a product on the basis of information concerning scratches and staining supplied from a wafer surface inspection device that detects the scratches and staining on the wafer surface on the basis of an LPD map, comprising:

input means for inputting the information concerning scratches and staining on the wafer that is supplied from the wafer surface inspection device;

memory means capable of accumulating the information concerning scratches and staining for each of a plurality of wafers; and

information processing means for detecting a type and degree of the scratches from characteristic quantities relating to the scratches in the information stored in the memory means, detecting a degree of the staining from characteristic quantities relating to this staining in the information stored in the memory means, and performing the judgement on the basis of criteria corresponding to the type and degree of the detected scratches and/or on the basis of criteria corresponding to the degree of the detected staining.

9. The judgement device according to claim 8, characterized in that the characteristic quantities relating to the scratches or staining are a depth and size of the scratches or staining.

10. The judgement device according to claim 8, characterized in that the characteristic quantities relating to the scratches constitute one or more items selected from a group consisting of a length, density, width, linearity, curvature and position of the scratches.

11. The judgement device according to claim 8, characterized in that the characteristic quantities relating to the staining constitute one or more items selected from a group consisting of an area, depth/density, distribution, shape and position of the staining.

12. A judgement method for judging whether or not a wafer that has scratches and staining on its surface is acceptable as a product on the basis of information concerning scratches and staining supplied from a wafer surface inspection device that detects the scratches and staining on the wafer surface on the basis of an LPD map, comprising the steps of:

detecting a type and degree of the scratches from characteristic quantities relating to scratches in the information, and detecting a degree of the staining from characteristic quantities relating to staining in the information; and

performing the judgement on the basis of criteria corresponding to the type and degree of the detected scratches and/or on the basis of criteria corresponding to the degree of the detected staining.

13. The judgement method according to claim 12, characterized in that the characteristic quantities relating to the scratches or staining are a depth and size of the scratches or staining.

14. A computer-readable memory medium which accommodates a program that includes a judgement step in which a type and degree of scratches are detected on the basis of characteristic quantities relating to the scratches in wafer surface information (information concerning scratches and staining on a wafer surface) that is supplied from a wafer surface inspection device, the degree of staining is detected on the basis of characteristic quantities relating to the staining in the surface information, and a judgement is made as to whether or not the wafer is acceptable as a product on the basis of criteria corresponding to the type and degree of the scratches and/or on the basis of criteria corresponding to the degree of the staining.

15. A wafer surface information processing device comprising:

input means for inputting wafer surface information (scratch information and staining information for a wafer surface) for respective wafers, that is supplied from a wafer surface inspection device;

memory means for accumulating the wafer surface information for each of a plurality of wafers;

superposing means for forming superposed surface information by superposing arbitrary wafer surface information accumulated in the memory means;

display means for displaying the superposed surface information formed by the superposing means; and

information processing means for processing various types of information.

16. The wafer surface information processing device according to claim 15, characterized in that the wafer surface information for each of the wafers and the superposed surface information are respectively displayed as images on the wafers.

17. The wafer surface information processing device according to claim 15 or claim 16, characterized in that the device is devised so that the judgement of the process in which scratches or staining have been generated can be supported by accumulating the wafer surface information in correspondence with wafer history information recording the processes through which each wafer has passed, and by outputting wafer surface information corresponding to the wafer history information.

18. The wafer surface information processing device according to claim 15 or claim 16, characterized in that the device is devised so that the judgement of the process in which scratches or staining have been generated can be supported by pre-recording the trend of particulars of generated defects for each process through which each wafer passes, and by outputting wafer surface information that matches this trend in particulars of generated defects.

19. A supporting device which is used to support the judgement of causes of generation of scratches and staining in wafer manufacturing processes, comprising input means, memory means, processing means and output means, and characterized in that the “

wafer surface information corresponding to wafer history information”

in the wafer surface information processing device according to claim 17 is extracted via the input means, the extracted “

wafer surface information corresponding to wafer history information”

is accumulated by the memory means, the processes in which scratches and staining are frequently generated are calculated by the processing means on the basis of the accumulated “

wafer surface information corresponding to wafer history information”

, and a result is output from the output means.

20. A supporting device which is used to support the judgement of a monetary amount to be covered by insurance during the conveyance of wafers, comprising input means, memory means, processing means and output means, and characterized in that the “

wafer surface information corresponding to wafer history information”

in the wafer surface information processing device according to claim 17 is extracted via the input means, the extracted “

wafer surface information corresponding to wafer history information”

is accumulated by the memory means, the monetary amount to be covered by insurance is calculated by the processing means on the basis of the accumulated “

wafer surface information corresponding to wafer history information”

, and a result is output from the output means.

24. The memory medium according to claim 22 or 23, which is a data base that is shared by a plurality of the devices according to any of claims 15 through 20.

21. A computer-readable memory medium which accommodates a program that includes a superposition step in which superposed surface information is formed by superposing wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a wafer surface inspection device.

22. A computer-readable memory medium which accommodates superposed surface information formed by superposing wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a wafer surface inspection device.

25. The memory medium according to any of claims 22 through 24, characterized in that required standards for wafers of specified wafer consumers are further accommodated.

23. A computer-readable memory medium which accommodates wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a wafer surface inspection device, and superposed surface information that is formed by superposing this wafer surface information.

26. A wafer surface information processing device comprising:

input means for inputting wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is respectively supplied from two wafer surface inspection devices;

memory means for accumulating the wafer surface information for each of a plurality of wafers;

superposing means for forming superposed surface information by superposing arbitrary wafer surface information accumulated in the memory means;

display means for displaying respective sets of wafer surface information or respective sets of superposed surface information of the two wafer surface inspection devices in contrast with each other; and

information processing means for processing various types of information.

27. The wafer surface information processing device according to claim 26, wherein the wafer surface information and the superposed surface information for each wafer are respectively displayed as images on the wafer.

28. The wafer surface information processing device according to claim 26 or claim 27, characterized in that the two wafer surface inspection devices are respectively disposed at a starting point and an end point of a certain wafer processing process.

29. The wafer surface information processing device according to claim 26 or claim 27, characterized in that the two wafer surface inspection devices are respectively disposed on the side of a wafer supplier and on the side of a wafer consumer.

34. The wafer surface information processing device according to claim 29, characterized in that a transmitting device which transmits data for wafers judged to be defective by the wafer consumer is disposed in the wafer surface inspection device located on the side of the wafer consumer.

35. The wafer surface information processing device according to claim 29, characterized in that a receiving device which receives data for wafers transmitted by the wafer consumer as a result of the wafers being judged to be defective is disposed in the wafer surface inspection device located on the side of the wafer supplier.

30. A wafer surface information processing device comprising:

input means for inputting wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a wafer surface inspection device that is disposed following a specified process that treats wafers;

memory means for accumulating the wafer surface information for each of a plurality of wafers;

superposing means for forming superposed surface information by superposing arbitrary wafer surface information accumulated in the memory means;

recording means for pre-recording a trend of particulars of generated defects in the process; and

output means for outputting the wafer surface information or the superposed surface information that matches the trend of particulars of generated defects,

characterized in that the device is devised so that it can be judged whether or not scratches and staining are generated in the process.

31. A computer-readable memory medium which accommodates wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a plurality of wafer surface inspection devices, and superposed surface information formed by superposing this wafer surface information, and which comprises a data base that is shared by a plurality of wafer surface information processing devices.

32. A computer-readable memory medium which accommodates wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from wafer surface inspection devices that are respectively disposed on the side of a wafer supplier and on the side of a wafer consumer, and superposed surface information formed by superposing this wafer surface information, and which comprises a data base that is shared by the wafer supplier and the wafer consumer.

33. A computer-readable memory medium which accommodates wafer surface information (scratch information and staining information for a wafer surface) for each wafer that is supplied from a wafer surface inspection device that is disposed following a specified process that treats wafers, superposed surface information formed by superposing this wafer surface information, and information which indicates a trend of particulars of generated defects in the process, and which comprises a data base that is shared by a plurality of wafer surface information processing devices.