Semiconductor memory device storing ternary data signal

• US 20040037108A1
• Filed: 01/07/2003
• Published: 02/26/2004
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Notani, Hiromi
• Granted Patent: US 6,795,333 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A memory cell in the SRAM has three storing/holding states, i.e., a state where two storage nodes store 0, 1; a state where the two storage nodes store 1, 0, and a state where the two storage nodes store 1, 1. Therefore, the number of memory cells can be reduced to a half compared to the conventional case where two memory cells were required to store three types of data signals.

Claims

1. A semiconductor memory device arranged at a crossing portion of a word line and first and second bit lines, comprising:

first and second inverters having output nodes connected to first and second storage nodes respectively;

a first switching circuit rendering conductive between said first storage node and an input node of said second inverter and applying a second potential to an input node of said first inverter if first and second potentials are applied to said first and second storage nodes respectively, rendering conductive between said second storage node and the input node of said first inverter and applying said second potential to the input node of said second inverter if said second and first potentials are applied to said first and second storage nodes respectively, and applying said second potential to each of the input nodes of said first and second inverters if said first potential is applied to each of said first and second storage nodes; and

a second switching circuit rendering conductive between said first bit line and said first storage node and between said second bit line and said second storage node, in response to said word line being set to a selective level.

2. The semiconductor memory device according to claim 1, wherein

said first and second potentials are a power-supply potential and a ground potential respectively;

and

said first switching circuit includes

a first P-channel MOS transistor connected between said first storage node and the input node of said second inverter and having a gate, electrode connected to said second storage node,

a second P-channel MOS transistor connected between said second storage node and the input node of said first inverter and having a gate electrode connected to said first storage node,

a first N-channel MOS transistor connected between the input node of said first inverter and a line of said ground potential, and having a gate electrode connected to said first storage node, and

a second N-channel MOS transistor connected between the input node of said second inverter and the line of said ground potential, and having a gate electrode connected to said second storage node.

3. The semiconductor memory device according to claim 1, wherein

said first and second potentials are a ground potential and a power-supply potential respectively;

and

said first switching circuit includes

a first N-channel MOS transistor connected between said first storage node and the input node of said second inverter, and having a gate electrode connected to said second storage node,

a second N-channel MOS transistor connected between said second storage node and the input node of said first inverter, and having a gate electrode connected to said first storage node,

a first P-channel MOS transistor connected between the input node of said first inverter and a line of said power-supply potential, and having a gate electrode connected to said first storage node, and

a second P-channel MOS transistor connected between the input node of said second inverter and the line of said power-supply potential, and having a gate electrode connected to said second storage node.

4. The semiconductor memory device according to claim 1, further comprising a read word line, first and second read bit lines, and a read circuit activated in response to said read word line being set to a selective level and reading a data signal held at said first and second storage nodes to apply the data signal to said first and second read bit lines.

5. The semiconductor memory device according to claim 4, wherein

said first and second read bit lines are pre-charged to a power-supply potential, and

said read circuit includes

first and second N-channel MOS transistors connected in series between said first read bit line and a line of a grounds potential, one of said first and second N-channel MOS transistors having agate electrode connected to said read word line the other one of said first and second N-channel MOS transistors having a gate electrode connected to the input node of said first inverter, and

third and fourth N-channel MOS transistors connected in series between said second read bit line and the line of said ground potential, one of said third and fourth N-channel MOS transistors having a gate electrode connected to said read word line, the other one of said third and fourth N-channel MOS transistors having a gate electrode connected to the input node of said second inverter.

6. The semiconductor memory device according to claim 4, wherein

said first and second read bit lines are pre-charged to a power-supply potential;

and

said read circuit includes

first and second N-channel MOS transistors connected in series between said first read bit line and a line of a ground potential, one of said first and second N-channel MOS transistors having a gate electrode connected to said read word line, the other one of said first and second N1 channel MOS transistors having a gate electrode connected to said first storage node, and

third and fourth N-channel MOS transistors connected in series between said second read bit line and the line of said ground potential, one of said third and fourth N-channel MOS transistors having a gate electrode connected to said read word line, the other one of said third and fourth N-channel MOS transistors having a gate electrode connected to said second storage node.

7. The semiconductor memory device according to claim 1, further comprising a match line, and a match/mismatch determination circuit determining whether or not a data signal held at said first and second storage nodes matches with a data signal applied to said first and second bit line, and applying a signal of a level according to a determination result to said match line.

8. The semiconductor memory device according to claim 7, wherein

said match/mismatch determination circuit determines that the data signal held at said first and second storage nodes matches with the data signal applied to said first and second bit lines if said first and second storage nodes have a same potential and/or if said first and second bit lines have a same potential.

9. The semiconductor memory device according to claim 7, wherein

said match line is pre-charged to a power-supply potential;

and

said match/mismatch determination circuit includes

first and second N-channel MOS transistors connected in series between said match line and a line of a ground potential, one of said first and second N-channel MOS transistors having a gate electrode connected to said first bit line, the other one of said first and second N-channel MOS transistors having a gate electrode connected to said first storage node, and

third and fourth N-channel MOS transistors connected in series between said match line and the line of said ground potential, one of said third and fourth N-channel MOS transistors having a gate electrode connected to said second bit line, the other one of said third and fourth N-channel MOS transistors having a gate electrode connected to said second storage node.

10. The semiconductor memory device according to claim 7, wherein

said match line is pre-charged to a power-supply potential;

and

said match/mismatch determination circuit includes

first and second N-channel MOS transistors connected in series between said match line and a line of a ground potential, one of said first and second N-channel MOS transistors having a gate electrode connected to said first bit line, the other one of said first and second N-channel MOS transistors having a gate electrode connected to an input node of said first inverter, and

third and fourth N-channel MOS transistors connected in series between said match line and the line of said ground potential, one of said third and fourth N-channel MOS transistors having a gate electrode connected to said second bit line, the other one of said third and fourth N-channel MOS transistors having a gate electrode connected to an input node of said second inverter.

11. The semiconductor memory device according to claim 1, further;

comprising a data detection line, and a data detection circuit determining whether or not both of said first and second storage nodes hold said first potential, and applying a signal of a level according to a determination result to said data detection line.

12. The semiconductor memory device according to claim 11, wherein

said first and second potentials are a power-supply potential and a ground potential respectively;

said data detection line is pre-charged to the power-supply potential; and

said data detection circuit includes

first and second N-channel MOS transistors having first electrodes both connected to said data detection line, second electrodes connected with each other, and gate electrodes connected to said first and second bit lines respectively, and

third and fourth N-channel MOS transistors connected in series between the second electrodes of said first and second N-channel MOS transistors and the line of said ground potential, and having gate electrodes connected to said first and second storage nodes respectively.

13. The semiconductor memory device according to claim 11, wherein

said first and second potentials are a ground potential and a power-supply potential respectively;

said data detection line is pre-charged to the power-supply potential; and

said data detection circuit includes

first and second N-channel MOS transistors having first electrodes both connected to said data detection line, second electrodes connected with each other, and gate electrodes connected to said first and second bit lines respectively, and

third and fourth N-channel MOS transistors connected in series between the second electrodes of said first and second N-channel MOS transistors and the line of said ground potential, and having gate electrodes connected to input nodes of said first and second inverters respectively.

14. The semiconductor memory device according to claim 1, further comprising a write circuit connected to said first and second bit lines and writing a data signal to said first and second storage nodes in said semiconductor memory device,

said write circuit including

a first tristate inverter applying an inversion signal of a first input signal to said first bit line if a write enable signal is at an activation level, and having an output node set in a high impedance state if said write enable signal is at an inactivated level, and

a second tristate inverter applying an inversion signal of a second input signal to said second bit line if said write enable signal is at an activated level, and having an output node set in a high impedance state if sad writing enable signal is at an inactivated level.

15. The semiconductor memory device according to claim 1, further comprising a read circuit connected to said first and second bit lines and reading a data signal held at said first and second storage nodes in said semiconductor memory device,

said read circuit including

a first comparison circuit comparing a potential of said first bit line with a reference potential between said first and second potentials, and outputting a signal of a level according to a comparison result, and

a second comparison circuit comparing a potential of said second bit line with said reference potential and outputting a signal of a level according to a comparison result.

16. The semiconductor memory device according to claim 15, further comprising a reference potential generating circuit generating said reference potential,

said reference potential generating circuit including

a switching element connected between a line of a power-supply potential and an output node, and rendered conductive in a pulsive manner at reading operation, and

a diode element connected between said output node and a line of a ground potential.