Thin film magnetic memory device conducting read operation and write operation in parallel

• US 20040037110A1
• Filed: 01/30/2003
• Published: 02/26/2004
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Granted Patent: US 6,839,272 B2
• Time in Patent Office: Days
• US Class Current: 365/171
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

Bit lines are provided corresponding to columns of MTJ memory cells. Word lines serving as read selection lines and write digit lines serving as write selection lines are provided corresponding to rows of MTJ memory cells. A word line decoder and a digit line decoder are independently provided for the word lines and the write digit lines. The word line decoder selectively activates a word line according to a read address applied to a read port. The digit line decoder selectively activates a write digit line according to a write address applied to a write port.

Claims

1. A thin film magnetic memory device, comprising:

a memory cell array including a plurality of magnetic memory cells each holding magnetically written storage data;

a first port for receiving a write address indicating a write selected memory cell which is selected for write operation in said memory cell array, and write data to said write selected memory cell;

a second port for receiving a read address indicating a read selected memory cell which is selected for read operation in said memory cell array, and outputting read data from said read selected memory cell; and

peripheral circuitry for conducting read operation and write operation in parallel in said memory cell array based on said read address and said write address, respectively.

2. The thin film magnetic memory device according to claim 1, wherein

said plurality of magnetic memory cells are arranged in a matrix,

said memory cell array further includes

a plurality of read selection lines and a plurality of write selection lines which are provided corresponding to memory cell rows, and

a plurality of bit lines provided corresponding to memory cell columns, and

said peripheral circuitry includes

a first decode circuit for selectively activating said plurality of read selection lines according to said read address,

a second decode circuit for selectively activating said plurality of write selection lines according to said write address,

a data read circuit for reading said storage data from said read selected memory cell by using one of said plurality of bit lines which is selected according to said read address, and

a data write circuit for writing said write data to said write selected memory cell by using one of said plurality of bit lines which is selected according to said write address.

3. The thin film magnetic memory device according to claim 2, wherein

said peripheral circuitry further includes a latch circuit for temporarily holding said write data as latch data until said write data is written to said write selected memory cell by said data write circuit,

when said read selected memory cell and said write selected memory cell are selected in parallel and correspond to the same bit line, said data write circuit postpones write operation to said write selected memory cell to a later cycle, and

said peripheral circuitry further includes a transfer circuit for outputting said latch data held in said latch circuit from said second port as said read data when an address corresponding to said latch data is designated by said read addresses.

4. The thin film magnetic memory device according to claim 2, wherein

said data write circuit supplies a first data write current corresponding to said write data to one of said plurality of bit lines which is selected according to said write address,

each of said plurality of write selection lines receives a second data write current of a predetermined direction when activated, and

said data write circuit starts supplying said first data write current after said second data write current starts being supplied to the write selection line corresponding to said write address, and completes supply of said first data write current before said supply of said second data write current is completed.

5. The thin film magnetic memory device according to claim 1, wherein

said memory cell array is divided into a plurality of banks,

each of said plurality of banks is capable of independently conducting said read operation or said write operation, and

said peripheral circuitry conducts said read operation from one of said plurality of banks and said write operation to another one of said plurality of banks in parallel.

6. A thin film magnetic memory device, comprising:

a memory cell array including a plurality of magnetic memory cells arranged in a matrix, each of said plurality of magnetic memory cells holding magnetically written storage data, wherein

said memory cell array further includes

a plurality of read selection lines and a plurality of write selection lines which are provided corresponding to memory cell rows,

a plurality of read bit lines provided corresponding to memory cell columns, and each electrically coupled to magnetic memory cells of corresponding one of said memory cell columns, and

a plurality of write bit lines provided corresponding to said memory cell columns, and each not being electrically coupled to said plurality of magnetic memory cells,

said thin film magnetic memory device further comprising;

a first port for receiving a write address indicating a write selected memory cell which is selected for write operation in said memory cell array, and write data to said write selected memory cell;

a second port for receiving a read address indicating a read selected memory cell which is selected for read operation in said memory cell array, and outputting read data from said read selected memory cell; and

peripheral circuitry for conducting read operation and write operation in parallel in said memory cell array based on said read address and said write address, respectively, wherein

said peripheral circuitry includes

a data read circuit for reading said storage data from said read selected memory cell by using at least one of said plurality of read bit lines which is selected according to said read address, and

a data write circuit for writing said write data to said write selected memory cell by using at least one of said plurality of write bit lines which is selected according to said write address.

7. The thin film magnetic memory device according to claim 6, wherein

said peripheral circuitry further includes

a first decode circuit for selectively activating said plurality of read selection lines according to said read address, and

a second decode circuit for selectively activating said plurality of write selection lines according to said write address.

8. The thin film magnetic memory device according to claim 6, wherein said data write circuit supplies a data write current corresponding to said write data to one of said plurality of write bit lines which corresponds to said write selected memory cell, and fixes each of the remaining write bit lines to a predetermined voltage.

9. The thin film magnetic memory device according to claim 6, wherein a distance between each of said plurality of memory cells and corresponding one of said plurality of write bit lines is shorter than a distance between each of said plurality of memory cells and corresponding one of said plurality of read bit lines.

10. A thin film magnetic memory device, comprising:

a plurality of memory blocks each including a plurality of magnetic memory cells arranged in a matrix, each of said plurality of magnetic memory cells holding magnetically written storage data, wherein

each of said plurality of memory blocks is capable of independently conducting read operation or write operation,

said thin film magnetic memory device further comprising;

a first port for receiving write data and a write address indicating a write selected memory cell to which said write data is to be written in said memory cell array;

a second port for receiving a read address indicating a read selected memory cell which is selected for read operation in said memory cell array, and outputting read data from said read selected memory cell; and

peripheral circuitry provided between said first and second ports and said plurality of memory blocks, for controlling said read operation and said write operation in said plurality of memory blocks, wherein

said peripheral circuitry includes a transfer circuit for writing said read data or said write data corresponding to one of said plurality of memory blocks to another one of said plurality of memory blocks in response to a transfer command.

11. The thin film magnetic memory device according to claim 10, wherein

said peripheral circuitry further includes

a plurality of read buses provided corresponding to said plurality of memory blocks, and each transmitting said read data from corresponding one of said memory blocks,

a plurality of write buses provided corresponding to said plurality of memory blocks, and each transmitting said write data to corresponding one of said memory blocks,

a first selector for selectively transmitting said write data from said first port to said plurality of write buses according to said write address, and

a second selector for selectively transmitting said read data from said plurality of read buses to said second port according to said read address, and

said transfer circuit includes a transfer bus for transmitting data between two memory blocks selected according to one of said read address and said write address.

12. The thin film magnetic memory device according to claim 11, wherein

each of said plurality of memory blocks is connected to another one of said plurality of memory blocks through said transfer bus, and

said peripheral circuitry further includes

a plurality of data read circuits and a plurality of data write circuits provided corresponding to said plurality of memory blocks,

a plurality of first transfer switch sections provided corresponding to said plurality of memory blocks, and each controlling connection between corresponding one of said data read circuits and corresponding one of said read buses and said transfer bus according to whether or not a read command and said transfer command from corresponding one of said memory blocks are applied, and

a plurality of second transfer switch sections provided corresponding to said plurality of memory blocks, and each controlling connection between corresponding one of said data write circuits and corresponding one of said write buses and said transfer bus according to whether or not a write command and said transfer command to corresponding one of said memory blocks are applied.

13. The thin film magnetic memory device according to claim 10, wherein

said peripheral circuitry further includes

a transfer control circuit for designating the memory block to which data is to be transferred as a transferred memory block or the memory block from which data is to be transferred as a transferring memory block, when said transfer command is executed, and

said transfer control circuit designates one of the memory block corresponding to said read selected memory cell and the memory block corresponding to said write selected memory cell as said transferring memory block according to whether or not said write operation and said read operation are conducted in parallel with said transfer command.